Method for planarized self-aligned floating gate to isolation

Details Method for planarized self-aligned floating gate to isolation Method for planarized self-aligned floating gate to isolation

1998-01-08

1999-12-28

Booth, Richard

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438692, H01L 218247

Patent

active

060081120

ABSTRACT:
A method for forming floating gate regions in non-volatile memory cells each having a floating gate and a control gate is disclosed. First, a plurality of isolation structures in a substrate extending above and below a surface of the substrate is formed. Second, a floating gate layer on the substrate over and between at least a portion of the isolation structures is formed. Finally, the floating gate layer is planarized down to the isolation structures for forming a plurality of the floating gate regions isolated by the isolation structures.

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