Method for planarized interconnect vias using electroless platin

Details Method for planarized interconnect vias using electroless platin Method for planarized interconnect vias using electroless platin

1997-10-27

2000-10-24

Talbot, Brian K.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438675, 438692, 427 97, 42725528, 427 98, 20419215, 20419217, B05D 512, H01L 214763, C23C 1432

Patent

active

061366935

ABSTRACT:
An improved and new method for fabricating conducting vias between successive layers of conductive interconnection patterns in a semiconductor integrated circuit has been developed. The method utilizes a first CMP step to form a barrier lined contact hole, deposition of copper by electroless plating into the barrier lined contact hole, and a second CMP step to remove overgrowth of copper, thus producing coplanarity between the copper surface and the surrounding insulator surface.

REFERENCES:
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patent: 5296407 (1994-03-01), Eguchi
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patent: 5656542 (1997-08-01), Miyata et al.
Palmans et al., Development of an elctroless copper deposition bath for via fill applications on TiN seed layers, Conference ProceedingsULSI-X, Materials Research Society, pp. 87-95, 1995.

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