Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2007-09-10
2011-11-15
Hassanzadeh, Parviz (Department: 1716)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S694000, C438S698000, C438S700000, C216S019000, C216S023000, C216S038000, C216S039000
Reexamination Certificate
active
08058175
ABSTRACT:
The invention discloses a planarization method for a wafer having a surface layer with a recess, comprises: forming an etching-resist layer on the surface layer to fill the entire recess; etching the etching-resist layer and the surface layer, till the surface layer outside the recess is flush to or lower than the bottom of the recess, the etching speed of the surface layer being higher than that of the etching-resist layer; removing the etching-resist layer; and etching the surface layer to a predetermined depth. The method can avoid concentric ring recesses on the surface of the wafer resulted from a chemical mechanical polishing (CMP) process in the prior art, and can be used to obtain a wafer surface suitable for optical applications.
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Chinese Office Action of related application mailed Jul. 18, 2008, 11 pgs. without translation.
Chen Yiqun
Han Yi'nan
Huang Herb He
Pu Xianyong
Hassanzadeh Parviz
Klunk Margaret D
Semiconductor Manufacturing International (Shanghai) Corporation
Squire Sanders & Dempsey (US) LLP
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