Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Utility Patent
1998-04-24
2001-01-02
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S783000, C438S784000, C438S760000, C438S909000
Utility Patent
active
06169026
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for the planarization of a semiconductor device, and more particularly to a method capable of preventing dopants from precipitating during the flow process of a deposited layer for the planarization.
2. Description of the Related Art
In semiconductor devices, active devices such as transistors, passive devices such as resistors, and a multilayer interconnection structure on the substrate are required. In the formation of the active device and passive device, the substrate surface can become uneven. Due to the high densification and high integration of the semiconductor device in recent years, the uneveness of the substrate surface has become conspicuous, and therefore more of a problem. It becomes more difficult to form a highly precise fine pattern. In addition, short-circuiting between the interconnections are also liable to occur. To solve these problems the technique for flattening the substrate surface is required.
Conventionally, a layer of insulating material such as silicon oxide is applied over such uneven surfaces, to permit the formation of a more finely patterned layer onto the surface of a non-planarized layer. This silicon dioxide layer, however, tends to conform to the underlying topography resulting in the creation of a non-planar or stepped surface. Accordingly, it is very difficult to form the more finely patterned layer on the uneven surface using a general lithography process.
Thus, there is provided a glass material such as spin-on-glass (SOG), and a material containing boron and/or phosphorous such as borosilicate glass (BPSG), phosphosilicate glass (PSG) and borosilicate glass (BSG) to be used for the formation of a planarized layer.
Among these layers for the planarization, for example a BPSG layer comprising boron of 3-5 wt % and phosphorous of 3-5 wt % is deposited on a semiconductor substrate having stepped layers thereon at a relatively low temperature of 400-450° C. Then, a thermal flow process for planarizing the BPSG layer deposited is performed at a temperature of 800-850° C., whereby a planarized surface is obtained. At this time, the BPSG layer acts as removing topology of the semiconductor substrate existing, for example, between a gate electrode and a first metal interconnection. As boron concentration (or weight fraction) in the BPSG layer increases, the flow temperature decreases. The degree of the planarization is also proportional to weight fraction of the boron and phosphorous atoms contained in the BPSG layer.
Referring to
FIG. 1
, a method for the planarization between a gate electrode and a first metal interconnection using BPSG layer according to the conventional art, is described.
A gate oxide film
3
, a gate electrode
4
, and junction regions are formed in and on a silicon substrate
1
(or wafer) with field oxide
2
for isolation of a device using a conventional method. Afterwards, sidewall spacers
6
are formed at both sides of the gate electrode
4
and then an interlevel insulating layer such as silicon dioxide is formed on the silicon substrate
1
by a chemical vapor deposition (CVD) method. Next, in order to even the overall surface topology due to height difference between the field oxide
2
and the gate electrode
4
, a BPSG layer
8
is formed on the interlevel insulating layer
7
by either plasma enhanced chemical vapor deposition (PECVD) or atmospheric pressure chemical vapor deposition (APCVD). As described above, it is preferable that the concentration of boron and phosphorous contained in the BPSG layer
8
be 3.5-5 wt % to achieve a more planar surface.
The wafer
1
on which the BPSG layer
8
is formed, is loaded into a diffusion furnace maintaining atmospheric pressure and a temperature of 750 to 850° C. Afterwards, the temperature of the diffusion furnace is elevated to 800-850° C., and nitrogen (N2) gas is supplied to the diffusion furnace. Under the above-mentioned conditions, a thermal annealing process for the flow of the deposited BPSG layer
8
deposited, proceeds for 20-60 minutes, whereby the BPSG layer
8
is planarized. Lastly, the temperature of the diffusion furnace is lowered to 650-800° C., and the wafer
1
is unloaded from the diffusion furnace.
Not shown in
FIG. 1
, a second insulating layer is then formed on the planarized BPSG layer
8
of the wafer
1
, and specific portions of the second insulating layer, the BPSG layer, and the first insulating layer are etched to expose the underlying junction regions, thereby forming contact holes. Afterwards, metal interconnections are formed to electrically contact with the exposed junction regions.
Then, boron and phosphorous atoms doped in the BPSG layer
8
diffuse out to the surface thereof during the flow process because of the high flow temperature. The diffused boron and phosphorous atoms are gathered to the surface of the BPSG layer
8
, whereby the surface thereof is over-saturated. Afterwards, when the wafer
1
is unloaded to the outside, the atoms gathered at the surface of the BPSG layer
8
are precipitated to crystal because of the abrupt change on the surface temperature and the moisture present in the atmosphere. These precipitated crystals generate not only crystal defects on the formation of a pattern but also pattern defects such as notching. Moreover, it degrades the insulating property of BPSG layer
8
.
SUMMARY OF THE INVENTION
Accordingly, it is one object of the present invention to provide a method for the planarization of a semiconductor device capable of preventing the generation of crystal defects by preventing dopants contained in BPSG layer for the planarization from precipitating when a wafer which BPSG layer is formed thereon, is unloaded from a diffusion furnace after the flow process of the deposited BPSG layer has been completed.
Another object of this invention is to provide a method for the planarization of a semiconductor device capable of facilitating the patterning of a layer that is deposited on BPSG layer.
According to the present invention, a method for the planarization of a semiconductor device comprises the steps of: providing a semiconductor substrate on which a patterned layer having topology is formed, into a reactor chamber; forming an interlevel insulating layer on the semiconductor substrate; forming a layer for the planarization containing a dopant on the interlevel insulating layer; diffusing the dopant contained in the layer for the planarization, outwards from the surface of the layer; pumping out the dopant diffused outwards from the layer for the planarization to the outside of the reactor chamber without introducing an inert gas to the reactor chamber;and flowing the layer for the planarization.
REFERENCES:
patent: 4239811 (1980-12-01), Kemlage
patent: 5094984 (1992-03-01), Liu et al.
patent: 5169801 (1992-12-01), Sato
patent: 5268333 (1993-12-01), Lee et al.
patent: 5286681 (1994-02-01), Maeda et al.
patent: 5314848 (1994-05-01), Yasui et al.
patent: 5424570 (1995-06-01), Sardella et al.
patent: 5461011 (1995-10-01), Hsue et al.
patent: 0519393 (1992-12-01), None
patent: 63-170928 (1988-07-01), None
patent: 1293632 (1989-11-01), None
patent: 3-237744 (1991-10-01), None
patent: 3273630 (1991-12-01), None
patent: 4-69954 (1992-03-01), None
patent: 6-29413 (1994-02-01), None
patent: 6232280 (1994-08-01), None
patent: 889427 (1988-09-01), None
patent: 9115046 (1991-08-01), None
patent: 93-11118 (1993-06-01), None
English translation of Abstract for KR93-11118 (Jun. 23, 1993).
Patents Abstracts of Japan, 4-69954, E-1221, Jun. 23, 1992 vol. 16, No. 280.
Patent Abstracts of Japan, 3-237744, E-1156, Jan. 20, 1992 vol. 16, No. 22.
English Translation of Purpose and Constitution of Korean Laid-Open No. 88-9427 (Sep.15, 1988).
English Translation of Purpose and Constitution of Korean Laid-Open No. 91-15046 (Aug.31, 1991).
“Silicon Nitride Isolation of Phosphosilicate Glass Layer,” by D. Woo, J. DiPiazza & S. Policastro, Technical Notes, sheets 1-2, a Publication of RCA, 1979.
Silicon Proc
Chung Yung Seok
Kim Eui Sik
Park In Ok
Booth Richard
Hyundai Electronics Industries Co,. Ltd.
Pompey Ron
LandOfFree
Method for planarization of semiconductor device including... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for planarization of semiconductor device including..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for planarization of semiconductor device including... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2469710