Method for planarization of an integrated circuit

Details Method for planarization of an integrated circuit Method for planarization of an integrated circuit

1993-12-28

1996-01-16

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

257635, H01L 2348, H01L 2946, H01L 2954, H01L 2962

Patent

active

054850355

ABSTRACT:
A method for planarization of an integrated circuit. After a first conducting layer is deposited and patterned, a first insulating layer is deposited over the device. A planarizing layer is then deposited over the integrated circuit and etched back. Portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the device. A second insulating layer is then deposited over the integrated circuit, followed by a third insulating layer. A contact via is formed through the layers to expose a portion of the first conducting layer. A second conducting layer can now be deposited and patterned on the device to make electrical contact with the first conducting layer.

REFERENCES:
patent: 3860836 (1975-01-01), Pederson
patent: 4613888 (1986-09-01), Mase et al.
patent: 4676867 (1987-06-01), Elkins et al.
patent: 5130782 (1992-07-01), Ashwell

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