Method for planarization

Semiconductor device manufacturing: process – Chemical etching – Combined with coating step

Reexamination Certificate

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C438S698000, C257SE21246

Reexamination Certificate

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07838427

ABSTRACT:
A method of planarizing a dielectric insulating layer including providing a substrate including forming a first dielectric insulating layer having a concave and convex portion on the substrate; forming an organic resinous layer on the first dielectric insulating layer and exposing the convex portion of the first dielectric insulating layer; isotropically etching the first dielectric insulating layer convex portion; removing the organic resinous layer; and, forming a second dielectric insulating layer on the first dielectric insulating layer.

REFERENCES:
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patent: 5139608 (1992-08-01), Grivna
patent: 5173448 (1992-12-01), Yanagi
patent: 5332687 (1994-07-01), Kuroda
patent: 5885900 (1999-03-01), Schwartz
patent: 6025270 (2000-02-01), Yoo
patent: 6281112 (2001-08-01), Sugiyama
patent: 6432827 (2002-08-01), Chien et al.
patent: 6617241 (2003-09-01), Doan
Quirk et al., Semiconductor Manufacturing Technology, Prentice-Hall, Upper Saddle River, New Jersey, 2001, pp. 519.

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