Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-05-12
2001-07-24
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06266803
ABSTRACT:
CROSS REFERENCE
TO APPENDIX INCLUDING COMPUTER PROGRAM LISTINGS Appendices A-H, which are integral parts of the present disclosure, include a listing of a computer program and its related data in one embodiment of this invention. This computer program listing contains material which is subject to copyright protection. The copyright owner, NexGen Microsystems Inc., which is also the Assignee of the present patent application, has no objection to the facsimile reproduction by anyone of the patent document or the present disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyrights whatsoever.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit designs. In particular, the present invention relates to the design of a distribution system for clock signals in an integrated circuit.
2. Discussion of the Related Art
“Clock skew” is a measure of uncertainty in the arrival times of a clock signal transition at different locations of a synchronous logic circuit, such as a microprocessor. Clock skews are undesirable since they adversely impact the operating frequency attainable by the logic circuit. Consequently, clock skews should be minimized. Clock skew can arise, for example, from RC delays in the interconnect wires between circuit elements, mismatches in the capacitive loads presented to clock buffers, and mismatches of driver sizes in clock buffers distributing the clock signals.
In the prior art, the clock distribution system (i.e. the placement of clock buffers and the routing of clock signals) in a full-custom microprocessor is often hand-crafted to minimize clock skew. Clearly, such procedure is time-consuming.
As the complexity of microprocessors grows, microprocessor designs have become “semi-custom”. In a semi-custom design, building blocks such as macros (e.g. regularly placed memory cells), arrayed logic elements (e.g. elements in data paths and register files) and standard cells (e.g. “random” logic) are used. Such building blocks are typically developed with automatic tools, such as logic synthesis, automatic placement and routing tools, which render the design task highly automated and efficient. However, as the design tasks are automated, hand-crafting the clock distribution system has become highly complex and impractical.
Clock distribution in a semi-custom design must take into account the nature of the various building blocks in the circuit. For example, within a custom macro block, the designer can still carefully place each transistor, route the wires for the clock signals and, where necessary, provide careful buffering of clock signals. In such a design, the designer can specify a “zero-skew” point, which is typically an entry point of the clock signal into the macro. Because the designer maintains control over placement and routing of the clock signals, clock skews within a custom macro block can usually be controlled by design decisions.
Arrayed logic elements, which are highly regular and with planned wiring locations built-in, allow a disciplined clock signal distribution strategy, as the total clock loading for the array and appropriate placements of clock buffers can be fairly accurately determined. Often, however, such arrayed logic element are placed and routed by automated tools. Such tools must be carefully directed to achieve the desired routing of clock signals.
Logic circuits built from standard cells belong to the most difficult class of circuits to route clock signals. Standard cell designs are primarily generated using a logic synthesis tool. In such a design, the designer provides the logic synthesis tool with a set of logic equations which express the desired logic circuit functionally. The synthesis tool then generates the implementation of the logic circuit, selecting circuit elements (e.g. logic gates) from a standard cell library. Various optimization techniques are typically applied to achieve such objectives as high cell density and gate minimization. Thus, the designer usually has no accurate means for predicting the sizes and locations of the capacitive loads driven by the clock signals, so that the number of clock buffers needed to adequately drive these capacitive loads and their optimal placements are not known in advance. Further, even for minor modification of the circuit, the logic synthesis tool often generates a radically different circuit topology for the circuit, such that a different clock distribution network may be required with each modification.
Because macros, arrayed logic and standard cells can often all be found in a semi-custom circuit, such as a microprocessor integrated circuit, it is desirable to have an automatic design tool which takes into account the different natures of these building blocks in placing clock buffers and routing clock signals, so as to achieve minimal clock skew in the integrated circuit.
SUMMARY OF THE INVENTION
The present invention provides a method for assigning clock buffers and routing clock signals to various regions of an integrated circuit with minimal clock skew. According to the present invention, a preassigned clock buffer area is allocated to each of various regions of an integrated circuit. In accordance to one aspect of the present invention, a method is provided which is particularly suited to assigning clock buffers in an area where the logic circuit is implemented by standard cells. According to this method, for each clock signal to be routed and for each row of the standard cells, the following steps are carried out: (a) identifying those standard cells receiving the clock signal, (b) associating an input capacitance with each of the identified standard cells, (c) for each identified standard cell, deriving a wire capacitance associated with the identified standard cell, the wire capacitance being derived by estimating a length of wire necessary to electrically couple the clock signal from the assigned buffer area to the identified standard cell, and (d) deriving a row capacitance by summing all of the input capacitances and the wire capacitances within the row of standard cells. Then, this method selects, in a predetermined order, each row of the standard cells, and performs, for the selected row of standard cells, the steps of (a) determining a window capacitance by summing row capacitances for selected rows of standard cells neighboring the selected row of standard cells, (c) determining a number of clock buffers to assign to the selected row of standard cells by dividing the window capacitance by the preferred load and a number derived from the number of the neighboring rows of standard cells, and (d) placing the number of clock buffers within the assigned buffer area.
The method of the present invention can be performed in conjunction with a sliding window moving from a row closest to one side of the area towards the opposite side of the area. In that approach, a predetermined number of neighboring rows of standard cells are included in the sliding window for each row of standard cells for which a clock buffer placement is considered. According to another aspect of the present invention, the output terminals of the clock buffers are strapped by wires running orthogonal to the standard cell rows. In one embodiment, the row capacitance is computed taking into consideration the per row capacitance of the strapping wire.
According to another aspect of the present invention, the method is also applicable to circuits implemented by arrayed logic or macros. In such a region where standard cells may not necessarily be included, the method of the present invention allocates an assigned buffer area, as before, and for each instance receiving the clock signal, whether the instance is built from macro or arrayed logic, the method (a) estimates an input capacitance of the instance associated with the clock signal, and (b) estimates a wire capacitance based on a length of wire needed to couple the clock signal from the assigned buffer area to the instance. In such a reg
Scherer Alisa M.
Weber Frederick
Advanced Micro Devices , Inc.
Kwok, Esq. Edward C.
Skjerven Morrill & MacPherson LLP
Smith Matthew
Thompson A. M.
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