Method for physical placement of an integrated circuit based...

Details Method for physical placement of an integrated circuit based... Method for physical placement of an integrated circuit based...

2008-01-08

2008-01-08

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07318211

ABSTRACT:
A method, system, apparatus, and machine-readable medium for physical placement of an integrated circuit based on the timing constraints are provided. The method involves a two-pass physical placement technique. After the first pass of the physical placements of the blocks and the top level, the timing results of the top level and of each block are analyzed. The method involves the computation of latency per gate per unit area (LPGA) of the block ports of each block. Based on the calculated LPGA, the timing constraints of the blocks are updated. The second pass of physical placement is performed, based on the updated timing constraints.

REFERENCES:
patent: 6845494 (2005-01-01), Burks et al.

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