Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
1999-12-27
2002-10-15
Jackson, Jerome (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
Reexamination Certificate
active
06465897
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates generally to alignment process in semiconductor manufacturing, and more particularly to the forming of alignment marks for photo alignment after CMP planarization.
(2) Description of the Related Art
Alignment marks and the process of aligning alignment marks are key aspects of fabricating integrate circuit (IC) chips in the manufacture of semiconductor components. They are key because the chips themselves and the devices that go into making the chip components are fabricated by aligning many intricate layers of conductors and insulators, one upon the other, on a substrate, usually silicon. And, in the resulting structure, called a wafer, it is critical that each layer is precisely aligned with the previous layer so that the circuits formed therein are functional and reliable.
Typically, the alignment of one layer with respect to another is accomplished by means of a tool known as a wafer stepper. The wafer stepper is used to project optically a circuit pattern from a reticle mounted in the wafer stepper onto a layer formed on the semiconductor wafer. However, before the pattern on the reticle is transferred, the wafer must first be positioned or aligned precisely with respect to the reticle. Thus, a wafer ready to be patterned is loaded onto a wafer stepper. Then, using the alignment marks already on the wafer, the wafer is aligned in relation to the reticle. Once the alignment is accomplished, the remaining steps of projecting the pattern on to the semiconductor may proceed.
As is well known in the art, the position of the alignment mark on the wafer is commonly sensed by means of a laser beam. The laser beam in the stepper is bounced off of the alignment mark to create a slonal pattern of laser light. The defraction from the mark is reflected back to sending devices in the stepper and is used as a signal to measure the exact position of the alignment mark. It is to be noted that the sensed quality of the detractive light from the alignment mark is directly dependent upon the integrity of the structure of the alignment mark. The present invention is concerned with that integrity, that is, with the structure and dimensions of alignment marks, that determine how well the alignment of semiconductor wafers is accomplished.
In general, alignment marks that are formed in a wafer are subjected to the same and many process steps that the rest of the wafer experiences. The steps include deposition of conductors, insulators, etching of the same, polishing, grinding and so on. After and before each one of these steps, the alignment mark must preserve its exact dimensions and be visible to the observing beam, such as the laser beam, so that alignment of various layers with respect to the mark will always be precisely repeatable.
Alignment marks (
20
) are usually of a simple geometrical shape such as a rectangle or a cross as shown in
FIG. 1
b,
and are commonly etched with a relatively shallow depth into the silicon substrate of wafer (
10
) shown in
FIG. 1
a.
The position of the alignment mark is sensed by the beam as it traverses edge (
21
) of mark (
20
), better seen in the cross-sectional view in
FIG. 2
a.
Therefore, the integrity of the edge dimension must be preserved throughout the various process steps of the wafer. The marks are formed into convenient areas on a wafer, such as a blank chip site (
13
′) inside a kerf (
11
), that is, inside trench like lines shown in
FIG. 1
a
that are scribed on a wafer around the perimeter of each chip site (
13
). The chips later on are broken off at the kerfs to separate them into individual components. When relatively thin and conformable materials such as oxides are deposited on a wafer, the alignment marks are also deposited with the material. However, because the deposited material is conformal, the exact shape and depth of the alignment mark is replicated. Consequently, the alignment beam can sense the exact step of the edge and hence the alignment mark. Even when the wafer is polished flat, as long as the material—such as the well known interlevel dielectrics, ILD—is transparent to the beam, the alignment mark in the layer below can still be seen and recognized. There are times, however, when materials, such as conductor metals, that are opaque to the observing beam are deposited over polished flat ILDs. In that case, the alignment mark is hidden below the metal layer and cannot be reckoned by the alignment system. Methods for circumventing these kinds of situations must be found, and though there are a few such prior art methods, not all of them address some unique problems that arise in the manufacture of semiconductor wafers, as discussed later.
In U.S. Pat. No. 5,401,691, Caldwell describes well some of the common problems encountered in prior art techniques of generating alignment marks and aligning wafers. Following his description, an alignment mark is generally. formed by etching a predetermined depth into the semiconductor
10
, as shown in
FIG. 2
a.
The etching process forms a step height over edge (
21
) in wafer (
10
). Step height acts as a measure of the alignment mark and is usually chosen to be some multiple of the wavelength of the laser light used by the stepper to conduct alignment. As is pointed out in U.S. Pat. No. 5,401, 691, by utilizing an alignment mark which is ¼ multiple of the laser wavelength, the signal to noise ratio of the laser diffraction is optimized, resulting in optimum alignment precision.
Next, the conventional steps of fabricating a semiconductor wafer are continued. Thus, subsequent layers used to form the integrated circuit are grown and deposited. For example, in
FIG. 2
b,
polysilicon conductor is deposited over the wafer as shown in
FIG. 2
b.
This step usually follows the growing of field isolation regions (not shown) elsewhere on the wafer where IC devices are formed. The polysilicon layer is then covered with the deposition of an ILD layer (
40
). Although the original alignment mark (
20
) is covered by subsequent layers, the step height (
21
) and therefore, the alignment mark (
20
) is replicated in the subsequently deposited layers. The replicated alignment marks are used for aligning and patterning the subsequent layers. That is, as more layers are added to the IC, the step height of the alignment mark is propagated upward or is “built upward” with subsequent layers. The step height of the alignment mark is therefore preserved in subsequent layers so that alignment of subsequent layer can be accomplished.
A problem that is well recognized with building up the alignment mark is its incompatibility with global planarization techniques, such as chemical-mechanical polishing (CMP). As more and more layers are added to the wafer manufacturing process, and circuit density increases, the requirement to planarize the wafer topography at intermediate steps in the process becomes essential. As is well known in the art, it is important to planarize surfaces of multilevel integrated circuits because nonplanar surfaces interfere with the optical resolution of subsequent photolithography processing steps. This makes it extremely difficult to print high resolution lines, as pointed out by Caldwell. Additionally, nonplanar surface topographies can effect subsequently formed metal layers. If a step height is too large, there is a serious danger that open circuits will be formed in later metal layers. It has been found in prior art that the best way to planarize the wafer topography is to planarize the ILDs and to use a global planarization technique, such as CMP. Global planarization techniques planarize the entire wafer surface and make the surface essentially flat. Unfortunately, when ILD (
40
) in
FIG. 2
b
is globally planarized, ILD all over the wafer including that which is over the alignment mark (
20
) is also planarized. The global planarization technique, therefore, removes the alignment mark replicated in ILD (
40
), as shown in
FIG. 2
c.
Although the alignment mark has been rem
Chang Jui-Yu
Shih Tsu
Ackerman Stephen B.
Cruz Lourdes
Oktay Sevgin
Saile George O.
Taiwan Semiconductor Manufacturing Company
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