Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-07-06
2003-08-12
Le, Thong (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S117000, C365S121000
Reexamination Certificate
active
06606261
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns a method for performing write and read operations. More particularly, the present invention relates to a method for performing read and write operations in a matrix-addressed memory array of memory cells comprising an electrically polarizable material exhibiting polarization remanence, in particular an electret or ferroelectric material, wherein a logical value stored in a memory cell is represented by an actual polarization state in the memory cell and is determined by detecting a charge flow to or from the cell in response to the application of voltages to the word and bit lines for addressing the memory cells of the array, wherein the charge flow detection in particular is based on detecting a charge flow component caused by a change of polarization in the polarizable material, and wherein write and read operations are performed under control of a control circuit device. The present invention also concerns an apparatus for performing the method; the apparatus including at least one matrix-addressed memory array of memory cells comprising an electrically polarizable material exhibiting polarization remanence, in particular a ferroelectric material, wherein logical value stored in a memory cell is represented by the polarization state in individual, separately selectable memory cells and determined by detecting a charge flow to or from the memory cells in response to an application of voltages to the word and bit lines for addressing the memory cells of an array, the charge flow detection in particular being based on a charge flow component caused by a change of polarization in said polarizable material.
2. Description of Related Art
Memory devices based on ferroelectric thin films are presently approaching a level of maturity where implementation in practical devices becomes possible. Two main types of device architectures are of relevance, involving either active or passive matrix addressing of the stored data.
In active matrix addressed architectures, each bit is stored in a memory cell consisting of a ferroelectric-filled capacitor structure with an associated dedicated microcircuit. The ferroelectric material is typically polarized in one of two stable states, representing a bit of information. The memory device comprises a large number of such cells, arranged in a matrix of conductors. Typically, the ferroelectric materials used in such devices are inorganic ceramics, e.g. perovskites.
In passive matrix addressed architectures, which are the ones of primary relevance in the present invention, the thin-film ferroelectric material is sandwiched between two orthogonal sets of electrodes such that a capacitor-like structure is formed in each overlap region between crossing electrodes. A bit is stored as a polarization state in the capacitor structure, which constitutes an elementary memory cell. No active circuitry is involved in connection with each cell, hence the term passive matrix addressing. This architecture is generally dependent on ferroelectrics with particular hysteresis properties, and at present only a few, organic based ferroelectrics have been identified as potentially useful in practice. The information is typically read destructively, i.e. by imposing an electric field that causes polarization alignment in the memory cells along the reading field direction.
In many applications, it is desirable to perform read/write operations in a given memory cell a large number of times, in which case the polarizable material is forced to undergo repeated polarization reversals and ultimately becomes fatigued. Fatigue manifests itself in different ways, most prominently as increased coercive field, lower remanent polarization and slower switching, all of which are highly undesirable in memory devices. Another phenomenon which complicates the readout process is imprint. When a cell is left in the same polarization state (i.e. logic state) for an extended time period, it may develop a tendency to be “frozen” into that state, such that the driving voltage must be increased and/or applied for a longer time in order to dislodge it and switch it to the other polarization direction.
Prior art reading protocols that employ read pulses of fixed length must take into account the large spread in cell switching speeds and polarization response that develops due to fatigue and/or imprint. Thus the pulses must have a high voltage and a long duration to be sure that the worst-case scenario could be handled. This is undesirable for several reasons. A high voltage implies higher cost and more space-demanding driving circuitry, more power consumption and increased cross-talk. Longer pulses imply lower data access and transfer speeds. Finally, employing long pulses at high voltage even to cells that are pristine or only moderately fatigued shall by itself contribute to accelerated fatigue.
Concrete examples of background art concerning methods for readout of data from a ferroelectric memory device, reference can be made to EP patent application No. 0 767 464 A2 (Tamura et al.) which in order to minimize disturbance of the logic state of a ferroelectric memory cell, applies a pulse voltage protocol which avoids large voltage excursions across the memory cell and the readout voltage protocol is moreover static with respect to temporal as well as amplitude aspects of the voltage pulses to be applied. Reference can further be made to U.S. Pat. No. 5,487,029 (Kuroda) which discloses the use of a refreshing procedure after a certain number of read/write operations applied to a memory cell has been executed, the refreshing procedure consisting of applying a polarization voltage V
p
higher than the write voltage V
0
. This ensures to remove a fatigue-induced reduction in the ferroelectric polarization and restore a higher polarization value of the memory cell. However, such a refreshing procedure will at best only be applicable in special instances, e.g. in the case where fatigue are due to charge accumulation and domain pinning because of shallow charge traps, but would be of little help in more complicated cases where deep charge traps, vacancy migration or when an irreversible chemistry at the electrodes are involved. It should moreover be noted that both the above-mentioned publications relate to active matrix-addressable memory devices only, whereas it would be desirable that the write/read protocols should be applicable to passive matrix-addressable memory devices as well.
BRIEF SUMMARY OF THE INVENTION
The present invention provides new methods for reading and writing data in memory devices based on electrically polarizable material, in particular ferroelectrics, whereby the polarization can be probed and controlled by methods that are less prone to create fatigue, yield faster data speeds and are less demanding of the driving circuitry than present-day alternatives.
The features of the present invention can be achieved with a method, which according to the invention, is characterized by recording a dynamic charge response of one or more of the memory cells during a write and read operation, by limiting a degree of polarization in the polarizable material during each write and read cycle to a value dependent on the recorded dynamic charge response and as defined by the control circuit device, and controlling the write and read operations according to an actual instantaneous charge response information with the value ranging from zero to an upper limit corresponding to the saturation magnitude of the polarization and being consistent with predetermined criteria for a reliable detection of a logic state of a memory cell.
In an embodiment of a method according to the invention, the stored logical value of a memory cell is determined by an application of one or more voltage pulses, the characteristics of which is controlled by the control circuit device.
In an embodiment of the invention addressing history can be established for the memory in terms of recorded exposure of the memory cells to fatigue and impri
Bröms Per
Gudesen Hans Gude
Johansson Mats
Nordal Per-Erik
Birch & Stewart Kolasch & Birch, LLP
Le Thong
Thin Film Electronics ASA
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