Method for performing verification of logic circuits

Details Method for performing verification of logic circuits Method for performing verification of logic circuits

2008-07-08

2008-07-08

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07398494

ABSTRACT:
The present invention relates to a method for verifying the proper operation of a digital logic circuit. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of:a) marking a net with an additional property other than a bit value, wherein both said bit value and said additional property are valid at said net at a given time;b) propagating the marking of the net according to a set of predetermined semantic rules, wherein the set of predetermined semantic rules are defined according to a predetermined simulation aim; andc) generating an output at a predetermined downstream location of the digital logic circuit, said output providing an information, if or if not said property has propagated through the circuit to said predetermined downstream location or not.

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