Method for performing timing closure on VLSI chips in a...

Details Method for performing timing closure on VLSI chips in a... Method for performing timing closure on VLSI chips in a...

2007-02-13

2007-02-13

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

10338929

ABSTRACT:
A method for performing timing closure on VLSI chips in a distributed environment is described. Abstracting the physical and timing resources of a chip and providing an asynchronous method of updating that abstraction allows multiple partitions of a chip to be optimized concurrently. A global view of physical and timing resources is supplied to local optimizations which are applied concurrently to achieve timing closure. Portions of the hierarchy are optimized in separate processes. Partitioning of the chip is performed along hierarchical lines, with each process owning a single partition in the hierarchy. The processes may be executed by a single computer, or spread across multiple computers in a local network. While optimizations performed by a single process are only applied to its given portion of the hierarchy, decisions are made in the context of the entire hierarchy. These optimizations include placement, synthesis, and routing. The present method can also be expanded to include other resources, such as routing resource, power supply current, power/thermal budget, substrate noise budget, and the like, all of which being able to be similarly abstracted and shared.

REFERENCES:
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5602754 (1997-02-01), Beatty et al.
patent: 5877965 (1999-03-01), Hieter et al.
patent: 6202192 (2001-03-01), Donath et al.

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