Method for performing timing analysis of a clock-shaping...

Details Method for performing timing analysis of a clock-shaping... Method for performing timing analysis of a clock-shaping...

1996-11-27

2001-02-06

Lintz, Paul R. (Department: 2768)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C703S019000, C703S014000, C703S015000, C703S016000

Reexamination Certificate

active

06185723

ABSTRACT:

TECHNICAL FIELD
This invention relates to a method for static timing analysis of integrated circuits, and more particularly, to a method for determining the timing of an output signal of a clock-shaping circuit.
BACKGROUND INFORMATION
A wide variety of design verification tools are required to produce a working integrated circuit from a functional specification. These tools analyze different parameters of a circuit design to insure that the circuit will function properly after it is fabricated. One important set of verification tools includes timing analysis tools which are widely used to predict the performance of very large scale integrated (VLSI) designs. Such timing analysis tools may be either static or dynamic. Dynamic timing analysis tools provide the most detailed and accurate information obtainable concerning the performance of a circuit. This type of timing analysis is often generated through simulation of a circuit model by simulation programs which operate at the transistor level. Examples of such circuit simulation programs are SPICE by University of California at Berkeley and ASTAP by IBM Corporation. These dynamic timing analysis programs typically operate by solving matrix equations relating to the circuit parameters such as voltages, currents, and resistances. Additionally, such circuit simulation approaches to performance analysis are pattern dependent, or stated another way, the possible paths and the delays associated therewith depend upon a state of a controlling mechanism or machine of the circuit being simulated. Thus, the result of a dynamic timing analysis depends on the particular test pattern, or vector, applied to the circuit.
While such circuit simulation programs and dynamic timing analysis tools provide high accuracy, long simulation times are required because a large number of patterns must be simulated because the best and worst case patterns are not known before the simulation occurs. In fact, a number of simulations which must be performed is proportional to 2
n
, where “n” is a number of inputs to the circuit being simulated. Thus, for circuits having a large number of inputs, dynamic timing analysis is not always practical.
Static timing analysis tools are also widely used to predict the performance of VISL designs. Static timing analyzers are often used on very large designs for which exhaustive dynamic timing analysis is impossible or impractical due to the number of patterns required lo perform the analysis. In static timing analysis, it is assumed that each signal being analyzed switches independently in each cycle of the state machine controlling that circuit. Furthermore, in static timing analysis, only the best and worst possible rising and falling times are computed for each signal in the circuit. The best and worst possible rising and falling times are typically determined in a single pass through a topologically sorted circuit. When referring to a topologically sorted circuit, it should be noted that a signal time associated with each point in the circuit being tested is determined in a sequential nature. Therefore, the signal time associated with the input of a first subcircuit whose output will be propagated to the input of a second subcircuit must be determined before the signal time associated with the input of the second subcircuit is calculated. Typical static analysis methods are described in “Timing Analysis of Computer Hardware,” by Robert B. Hitchcock, Sr., et al.,
IBM J Res. Develop
., Vol. 26, No. 1, pp. 100-105 (1982), which is incorporated by reference herein.
Static timing analysis may be applied to a simple two input NAND circuit
100
such as that illustrated in FIG.
1
. Typically, cells such as the one shown in
FIG. 1
are kept in cell libraries and may be used as building blocks by designers to construct larger and more complex integrated circuits. Typically, for each cell in a cell library, a dynamic timing analysis has already been performed and the timing parameters of the cell are maintained as part of the cell description. In the example shown, NAND circuit
100
is known to have a minimum delay of 30 picoseconds, and a maximum delay of 40 picoseconds, for a rising edge received at an inputs A and B. Thus, if it is known that a rising edge will be received at input A at sometime between 10 and 20 picoseconds measured from an initial time p0, then the earliest output will be a falling edge at output C at 40 picoseconds and a latest falling edge at output C at 60 picoseconds from time, p0. Since in any given cycle a data signal on input B can be either high or low, input B is ignored when computing the delay from input A to the output C. Thus, the timing computed for the circuit is described in terms of minimum and maximum signal switching times and is independent of the actual pattern received at the inputs.
Transistor-level timing analyzers eliminate the need for predefined cell libraries by decomposing circuits into channel-connected components and automatically computing the delay of each component. Such channel connected components are non-intersecting groups of transistors which are connected by source and drain terminals to one another and to supply and ground nets, or connections. Each channel connect component can be analyzed independently to compute the worst case delays from each input to each output for both rising and falling signals. Details of such delay calculation techniques are well-known to those with skill in the art. For more information, refer to “Timing Analysis and Performance Improvement of MOS VLSI Designs,” by Jouppi,
IEEE Transactions on Computer-Aided Design
, Vol. 6, No. 4 (1987), and “Crystal: A Timing Analyzer for NMOS VLSI Circuits,” by Ousterhout, Proc. 3rd Cal. Tech. VLSI Conf., Computer Science Press, pp. 57-69 (1983), each of which is incorporated herein by reference.
Although the traditional transistor level static timing analysis approach works well for many logic circuits, this approach typically overly constrains the timing associated with clock-shaping circuits. Clock-shaping circuits are common in memory arrays such as caches where precise signal timing is required. Specifically, clock-shaping circuits are provided to widen or narrow a clock pulse. A typical clock-shaping circuit is illustrated in FIG.
2
. The timing associated with the clock-shaping circuit is illustrated in FIG.
3
. As is illustrated in
FIG. 3
, the signal C
0
′ is a delayed version of an input clock signal, C
0
. When the C
0
′ signal is combined with the C
0
signal at a NOR gate
202
, a C
1
output signal is produced. Similarly, when the C
0
′ signal is combined with the C
0
signal at NAND gate
204
, the C
2
signal is generated. As illustrated in
FIG. 3
, the C
1
signal output from NOR gate
202
produces a narrowed pulse and the C
2
signal output by NAND gate
204
produces a widened pulse.
When the prior art (static timing analysis) methodologies are implemented to determine the timing associated with the clock-shaping circuit, the signal event times illustrated in
FIG. 4
are computed. In the timing diagram of
FIG. 4
, the hashed areas represent regions of uncertainty between the maximum and minimum possible signal event times. In
FIG. 4
, the functions of NOR gate
202
and NAND gate
204
are essentially ignored because the signal timing is computed in a pattern-independent way. This pattern independence is necessary when the gate inputs are data signals that can have arbitrary combinations of values. However, when the inputs are clock signals, they can be expected to switch in predictable ways and the worst-case times computed using a pattern-independent analysis can be unnecessarily pessimistic. These clock signals are usually used to synchronize signal flow through data paths in a digital circuit. If the clock signals are reshaped, it is to adjust their timing to allow some path or paths to meet timing constraints that would be violated with the original clock signal. The excess pessimism of the pattern-independent analysis of the reshaped clock will t

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