Method for performing post-synthesis circuit optimization

Details Method for performing post-synthesis circuit optimization Method for performing post-synthesis circuit optimization

2006-10-09

2010-02-16

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07665047

ABSTRACT:
Two methods for post-synthesis circuit optimization are disclosed. In both methods, the underlying variability in process parameters is captured through a robust linear program. The robust linear program is then reformulated as a second order conic program that possesses special structural properties to allow for a computationally efficient solution by using interior point optimization methods. The first method treats gate delays as uncertain quantities and obtains the optimal sizes for gates in a circuit under a probabilistically specified circuit timing target. The second method optimizes total circuit power by using a combination of dual threshold voltage assignment and gate sizing. Both circuit power and timing are treated probabilistically.

REFERENCES:
patent: 3083562 (1963-04-01), Weizer

Affiliated with

Also associated with

Rating

Method for performing post-synthesis circuit optimization does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for performing post-synthesis circuit optimization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for performing post-synthesis circuit optimization will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4181484