Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-07-29
2008-07-29
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
11243839
ABSTRACT:
The present invention provides a method for performing design rule check (DRC) of an integrated circuit. A design layout of the integrated circuit is provided. The integrated circuit includes a complex circuit. A DRC tool is used to compare a portion of the design layout with a reference layout containing an accurate implementation of the complex circuit. The portion of the design layout corresponds to the complex circuit.
REFERENCES:
patent: 6009251 (1999-12-01), Ho et al.
patent: 6418551 (2002-07-01), McKay et al.
patent: 6505327 (2003-01-01), Lin
patent: 6560766 (2003-05-01), Pierrat et al.
patent: 6606735 (2003-08-01), Richardson et al.
patent: 6721928 (2004-04-01), Pierrat et al.
patent: 6756242 (2004-06-01), Regan
patent: 6883149 (2005-04-01), Li et al.
patent: 6892368 (2005-05-01), Li et al.
patent: 6941530 (2005-09-01), Joshi et al.
patent: 6948145 (2005-09-01), Brown et al.
patent: 7082588 (2006-07-01), Scheffer et al.
patent: 7096439 (2006-08-01), Tsai et al.
patent: 7155689 (2006-12-01), Pierrat et al.
patent: 7162703 (2007-01-01), Aik
patent: 7171639 (2007-01-01), Genz et al.
patent: 2001/0052107 (2001-12-01), Anderson et al.
patent: 2002/0026621 (2002-02-01), Mukai
patent: 2002/0100005 (2002-07-01), Anderson et al.
patent: 2002/0138813 (2002-09-01), Teh et al.
patent: 2003/0061583 (2003-03-01), Malhotra
patent: 2003/0182645 (2003-09-01), Fairbanks
patent: 2003/0196180 (2003-10-01), Li et al.
patent: 2004/0088660 (2004-05-01), Tran
patent: 2004/0199880 (2004-10-01), Kresh et al.
patent: 2005/0076316 (2005-04-01), Pierrat et al.
patent: 2005/0086619 (2005-04-01), Teh et al.
patent: 2005/0223347 (2005-10-01), Okuaki
patent: 2006/0265675 (2006-11-01), Wang
Corbeil, Jr. John D.
Saunders Michael J.
LSI Corporation
Suiter Swantz PC LLO
Whitmore Stacy A
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