Method for performing dead-zone quantization in a single process

Details Method for performing dead-zone quantization in a single process Method for performing dead-zone quantization in a single process

1997-03-06

1998-12-01

Ellis, Richard L.

Boots, shoes, and leggings

36472503, G06F 9302

Patent

active

058451129

ABSTRACT:
An extension to existent vector instruction sets is presented in a form of new vector instructions which perform operations specialized for efficient digital video compression and decompression. A processor is designed to implement the arithmetic operation of each of these instructions in a single clock cycle, and some of the present instructions perform arithmetic operations selectively and directly on elements of the same registers.

REFERENCES:
patent: 5345408 (1994-09-01), Hoogenboom
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Neogi et al., Embedded Parallel Divide-and-Conquer Video Decompression Algorithm and Architecture for HDTV Applications, IEEE Transactions on Consumer Electronics, vol. 41, No. 1, Feb. 1995, pp. 160-171.
Araki et al., Video DSP Architecture for MPEG2 CODEC, IEEE 1994, pp. II-417 to II-420.
Ramaswamy et al., Efficient Implementation of the Two Dimensional Discrete Cosine Transform for Image Coding applications on the DSP96002 Processor, IEEE 1993, pp. 96-99.
Fandrianto et al., A Programmable Solution for Standard Video Compression, IEEE 1992, pp. 47-50.

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