Method for performing branch prediction and resolution of two or

Electrical computers and digital processing systems: processing – Processing control – Branching

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712239, 712 23, G06F 1560

Patent

active

06157998&

ABSTRACT:
A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.

REFERENCES:
patent: 4200927 (1980-04-01), Hughes et al.
patent: 4775927 (1988-10-01), Hester et al.
patent: 5860017 (1999-01-01), Sharangpani et al.
patent: 5903918 (1999-05-01), Bauman et al.
patent: 6029240 (2000-02-01), Blaner et al.

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