Method for patterning polysilicon gate layer based on a photodef

Details Method for patterning polysilicon gate layer based on a photodef Method for patterning polysilicon gate layer based on a photodef

1997-12-30

2000-10-17

Tsai, Jey

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438591, 438593, 438949, H01L 213205

Patent

active

061331287

ABSTRACT:
A process for patterning a gate of a semiconductor device is provided. A gate material layer is formed upon an oxide layer of a substrate. A photoresist layer is formed upon the gate material layer. A portion of the photoresist layer is photo-oxidized. The portion defines a gate pattern. The portion of the photoresist layer is converted into a hard mask. A portion of the gate material layer is patterned with the hard mask. The portion of the gate material layer defines a gate.

REFERENCES:
patent: 5960270 (1999-09-01), Misra et al.
Joubert, Application of Plasma Polymerized Methylsilane in all dry resist for 193 and 248nm lithography,Microelectronic engineering, 1996.

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