Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2002-06-28
2004-01-13
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S734000, C438S736000
Reexamination Certificate
active
06677240
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of electronic devices and more particularly to a method for patterning dense and isolated features on a semiconductor device.
BACKGROUND OF THE INVENTION
In an effort to further miniaturize semiconductor devices, there is a continuing drive to reduce the width of the holes and features on the silicon surface. As the width of the holes and features get smaller than the wavelength of the particular radiation source used in the patterning process, diffraction may cause patterning errors. To correct this problem, the process of Optical Proximity Correction is used. Optical Proximity Correction refers to adjusting patterns of the holes and/or features on the mask by the margin of error caused by the diffraction effect so that the actual pattern provided on the silicon surface is closer to the desired pattern. However, Optical Proximity Correction is inadequate where a mask defines a combination of densely populated holes/features and isolated holes/features. This is because Optical Proximity Correction cannot completely compensate for the differences in isolated and dense holes/features. So there remains an intolerable depth of focus variation between the dense and isolated holes/features. This problem is worsened as the holes/features are further miniaturized.
To overcome this problem, lithographers use two separate masks having critical patterns to pattern features on a single level—one mask having critical patterns of densely populated holes/features and the other mask having critical patterns of isolated holes/features. Although this technique alleviates the problem of focus depth variation between dense and isolated holes/features, it creates a separate problem for aligning the patterned level with other layers of the semiconductor device. For example, aligning contacts of the patterned level to the underlying level using the imprint of one mask as a reference creates an error in alignment of contacts formed according to the second mask.
SUMMARY OF THE INVENTION
According to one embodiment of the invention, a method of forming a semiconductor device is provided. The method includes providing a first mask that defines a densely populated plurality of hole patterns. The first mask overlies a layer of dielectric material. The method also includes defining at least one isolated hole pattern in the first mask by covering one or more of the defined densely populated hole patterns using a second mask. The method also includes forming a plurality of densely populated holes in the dielectric material and at least one isolated hole by etching, according to one or more of the plurality of hole patterns that are not covered by the second mask, the layer of dielectric material.
Some embodiments of the invention provide numerous technical advantages. Some embodiments may benefit from some, none, or all of these advantages. For example, according to one embodiment, the error caused by having two mask alignment references is eliminated by providing only one mask having a critical pattern. According to another embodiment, patterning of features is simplified because only one critical pattern is required rather than two. According to another embodiment, any transitional area between the dense and isolated groups of features is eliminated by presenting a uniform density on a single critical mask.
Other technical advantages may be readily ascertained by one of skill in the art.
REFERENCES:
patent: 6150256 (2000-11-01), Furukawa et al.
Brady III W. James
Fahmy Wael
McLarty Peter K.
Peralta Ginette
Telecky , Jr. Frederick J.
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