Semiconductor device manufacturing: process – Forming schottky junction – Using platinum group metal
Reexamination Certificate
2001-10-29
2003-03-25
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Forming schottky junction
Using platinum group metal
C438S003000, C438S240000, C438S686000, C438S651000
Reexamination Certificate
active
06537900
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for patterning a metal or metal silicide layer, and to a high-epsilon dielectric or ferroelectric capacitor in an integrated semiconductor circuit.
Conventional microelectronic memory elements (DRAMs) include a capacitor in which the information to be stored is stored in the form of a charge. Silicon oxide or silicon nitride layers having a dielectric constant of at most about 8 are usually used as a capacitor material. “Novel” capacitor materials (dielectrics or ferroelectrics) having significantly higher dielectric constants are required for reducing the size of the storage capacitor and also for fabricating non-volatile memories (FeRAMs).
A number of capacitor materials suitable for this purpose—Pb(Zr, Ti)O
3
[PZT], SrBi
2
Ta
2
O
9
[SBT], SrTiO
3
[ST] and (Ba, Sr)TiO
3
[BST]—are specified in the article “Neue Dielektrika {umlaut over (fur)} Gbit-Speicherchips” [New dielectrics for Gbit memory chips] by W. Hönlein, Phys. Bl. 55 (1999), pages 51-53.
The use of such novel high-epsilon dielectrics/ferroelectrics gives rise to the difficulty that Si, the traditional electrode material, can no longer be used since it is not compatible with the oxidizing atmosphere required during the dielectric/ferroelectric deposition or heat treatment.
Appropriate electrode materials are primarily sufficiently inert metals and metal silicides. The patterning of such layers has, however, hitherto remained a largely unresolved problem since suitable etching gases for removing such layers are not known at the present time.
The article “Silicid-Mikrostrukturen durch lokale Oxidation” [Silicide microstructures by local oxidation] by S. Mantl, Phys. Bl. 51 (1995), pages 951-953, proposes patterning silicide layers by locally oxidizing the layer in order to fabricate buried interconnects and mesa structures made of metal silicide. On the other hand, a method for forming platinum silicide is disclosed e.g. in U.S. Pat. No. 5,401,677.
U.S. Patent No. U.S. Pat. No. 5,561,307 describes a ferroelectric capacitor in an integrated circuit, whose base electrode is formed from a Pt layer by means of an RIE (Reactive Ion Etching) process. However, the RIE process exhibits an unsatisfactory selectivity with respect to mask materials and Pt substrates and does not allow the fabrication of a base electrode with a well-defined edge profile.
Published European Patent Application EP 0 867 926 A1 describes a method for fabricating a capacitor electrode made of a platinum-group metal. In this method, a metal layer is applied to a substrate partly made of a:Si and partly made of tungsten nitride and is silicided in a subsequent heat treatment step. The silicided layer sections are removed, with the result that an electrode made of platinum remains above the tungsten nitride layer region.
Published German Patent Application DE 195 03 641 A1 describes a method for patterning a metal silicide layer in which an Si
3
N
4
mask covering the metal silicide layer is used for predetermining the structure. The substrate is unpatterned Si.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a high-epsilon dielectric or ferroelectric capacitor structure having a metal or metal silicide electrode, and a method for patterning a metal or metal silicide layer which overcomes the above-mentioned disadvantages of the prior art apparatus and methods of this general type. In particular, it is an object of the invention to provide a method for patterning a metal or metal silicide layer that enables, in a technologically simple manner, the fabrication of a high-epsilon dielectric or ferroelectric capacitor with a metal or metal silicide electrode in an integrated circuit. Furthermore, it is an object of the invention to fabricate a high-epsilon dielectric or ferroelectric capacitor structure having a metal or metal silicide electrode with a well-defined edge profile.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for patterning a metal layer, which includes steps of: providing a substrate; above the substrate, producing a patterning layer for structuring a structuring pattern; producing the patterning layer with a base layer zone and a sinking layer zone laterally surrounding the base layer zone, the base layer zone having a contour; depositing a metal layer onto the patterning layer; siliciding the metal layer, at least in a region of the metal layer lying on the sinking layer zone such that a metal silicide layer section is formed in the region; and performing an oxidation step such that the metal silicide layer section migrates into the sinking layer zone of the patterning layer and a metal region having a contour that is identical to the contour of the base layer zone remains on the base layer zone.
With the foregoing and other objects in view there is also provided, in accordance with the invention, a method for patterning a metal silicide layer, which includes steps of: providing a substrate; above the substrate, producing a patterning layer for structuring a structuring pattern; producing the patterning layer with a base layer zone and a sinking layer zone laterally surrounding the base layer zone, the base layer zone having a contour; producing a metal silicide layer on the patterning layer; performing an oxidation step to oxidize the metal silicide layer at least in a section of the metal silicide layer in the sinking layer zone where the metal silicide layer migrates into the sinking layer zone; and during the oxidation step, a region of the metal silicide layer having a contour identical to the contour of the base layer zone remains on the base layer zone.
In general, the invention is based on burying, below an oxide, undesired regions of the unpatterned metal or metal silicide layer from which e.g. a base electrode for a capacitor is intended to be formed, instead of removing them in the hitherto customary manner by means of chemical or physical processes.
For this purpose, according to the invention, first a patterning layer with a pattern (prepatterned base layer zone) of the patterned metal layer to be formed is produced. Since the patterning layer can be realized from customary layer materials that are technologically simple to handle (Si, in particular polysilicon in the sinking layer zone; for example SiO
2
in the base layer zone), this layer can be produced without difficulty using the customary planar-technology methods (layer deposition methods; layer patterning by lithography and etching techniques).
The prepatterned base layer zone preferably has a structure that is identical in relation to the metal layer (metal region) to be patterned. In other words, the base layer zone serves as a mask of the metal region to be formed, which is intended to be created by patterning the metal layer.
According to a first aspect of the invention, a metal layer is deposited above the patterning layer. The undesired regions of the metal layer which lie laterally outside the base layer zone are silicided and subsequently “sunk” in the patterning layer by oxidation.
In this way, it is possible to form a patterned metal layer which includes metal to the greatest possible extent over the whole area and serves as an electrode, metallization layer or interconnect.
In particular, the patterned metal layer includes a patterned metal region which is essentially of the same structure in relation to the base layer zone, i.e. the outer contour of the base layer zone corresponds to the contour of the patterned metal region. In this case, in contrast to the lateral, sunk metal silicide layer section, the metal region produced is not altered in terms of its position, but can also be partially or completely silicided.
When a metal layer is deposited, it is also possible, however, to produce a patterned metal region which includes metal silicide over part of or the whole area. In this case, regions above the base layer
Mazure-Espejo Carlos
Schindler Günther
Weinrich Volker
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Nguyen Tuan H.
Stemer Werner H.
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