Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2005-11-22
2005-11-22
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S005000, C327S143000
Reexamination Certificate
active
06968484
ABSTRACT:
A method is described for parametrizing an integrated circuit by applying a digital start command signal followed by a parametrization data signal to the supply voltage terminal and/or the output terminal of the integrated circuit. During the parametrization process, the voltage level applied to the supply voltage terminal and/or the output terminal is kept above the normal operating voltage level and detected by a detector device provided in integrated circuit. The integrated circuit includes the supply voltage terminal, a reference potential terminal, and the output terminal, as well as an internal memory which is preferably non-volatile. The adjustment specification for parametrizing the integrated circuit is stored in the memory and activated by the parametrization data signal.
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Foley & Hoag LLP
Kamholz Scott E.
Lamarre Guy J.
Micronas GmbH
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