Method for parallel programming of nonvolatile memory devices, i

Details Method for parallel programming of nonvolatile memory devices, i Method for parallel programming of nonvolatile memory devices, i

1998-10-27

2000-05-30

Dinh, Son T.

Static information storage and retrieval

Floating gate

Particular biasing

36518518, 36518519, G11C 1606

Patent

active

060698225

ABSTRACT:
The programming method comprises the steps of applying a programming pulse to a first cell and simultaneously verifying the present threshold value of at least a second cell; then verifying the present threshold value of the first cell and simultaneously applying a programming pulse to the second cell. In practice, during the entire programming operation, the gate terminal of both the cells is biased to a same predetermined gate voltage and the source terminal is connected to ground; the step of applying a programming pulse is carried out by biasing the drain terminal of the cell to a predetermined programming voltage and the step of verifying is carried out by biasing the drain terminal of the cell to a read voltage different from the programming voltage. Thereby, switching between the step of applying a programming pulse and verifying is obtained simply by switching the drain voltage of the cells.

REFERENCES:
patent: 5422842 (1995-06-01), Cernea et al.
patent: 5495442 (1996-02-01), Cernea et al.
patent: 5521864 (1996-05-01), Kobayashi et al.
patent: 5532964 (1996-07-01), Cernea et al.
patent: 5784318 (1998-07-01), Anami
patent: 5787038 (1998-07-01), Park
patent: 5864503 (1999-01-01), Pascucci

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