Method for parallel processing of dram read request in a memory-

Details Method for parallel processing of dram read request in a memory- Method for parallel processing of dram read request in a memory-

1996-02-09

1999-02-16

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

395309, 711168, G06F 1202

Patent

active

058731199

ABSTRACT:
A syncDRAM memory interface is provided that is capable of extending data burst during a data transfer in a syncDRAM memory so as to provide a continuous draw of data from the syncDRAM memory banks. Included in the interface is a pipeline request path configured to receive pipeline request data from a microprocessor, a pipeline command generator configured to generate pipeline commands and transfer them to the syncDRAM memory such that a pipeline data transfer command is transferred to the syncDRAM memory in parallel with a primary command generated from the microprocessor and sent to the syncDRAM. This pipeline data transfer command is received by the syncDRAM through the same internal address latch used in response to a primary data transfer request. A pipeline arm generator is also provided to communicate with the pipeline request path and the data transfer controller to indicate that the syncDRAM interface is ready to transfer data in response to a pipeline request.

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