Method for page sharing in a processor with multiple threads...

Details Method for page sharing in a processor with multiple threads... Method for page sharing in a processor with multiple threads...

2007-02-20

2007-02-20

Peikari, B. James (Department: 2189)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C712S215000, C711S206000, C711S203000

Reexamination Certificate

active

10650335

ABSTRACT:
A method and system for allowing a multi-threaded processor to share pages across different threads in a pre-validated cache using a translation look-aside buffer is disclosed. The multi-threaded processor searches a translation look-aside buffer in an attempt to match a virtual memory address. If no matching valid virtual memory address is found, a new translation is retrieved and the translation look-aside buffer is searched for a matching physical memory address. If a matching physical memory address is found, the old translation is overwritten with a new translation. The multi-threaded processor may execute switch on event multi-threading or simultaneous multi-threading. If simultaneous multi-threading is executed, then access rights for each thread is associated with the translation.

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