Method for packaging semiconductor dies having...

Details Method for packaging semiconductor dies having... Method for packaging semiconductor dies having...

2007-07-16

2010-11-02

Chu, Chris (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257SE23181, C257S698000, C257S777000, C438S118000

Reexamination Certificate

active

07825517

ABSTRACT:
An integrated circuit structure is provided. The integrated circuit structure includes a die and an anisotropic conducing film (ACF) adjoining the back surface of the die. The die includes a front surface; a back surface on an opposite side of the die than the front surface; and a through-silicon via (TSV) exposed through the back surface of the die.

REFERENCES:
patent: 6429096 (2002-08-01), Yanagida
patent: 6667542 (2003-12-01), Yamaguchi et al.
patent: 6794751 (2004-09-01), Kumamoto
patent: 7098076 (2006-08-01), Liu
patent: 7169648 (2007-01-01), Sato et al.
patent: 7279776 (2007-10-01), Morimoto
patent: 7537959 (2009-05-01), Lee et al.
patent: 7588964 (2009-09-01), Kwon et al.
patent: 2007/0158787 (2007-07-01), Chanchani
patent: 1591884 (2005-03-01), None
patent: 1937216 (2007-03-01), None
patent: 2006/012737 (2006-01-01), None

Affiliated with

Also associated with

Rating

Method for packaging semiconductor dies having... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for packaging semiconductor dies having..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for packaging semiconductor dies having... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4187467