Method for packaging semiconductor device having bump...

Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate

Reexamination Certificate

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Details

C438S942000, C438S945000, C427S096400, C118S255000, C430S005000, C430S308000, C430S324000

Reexamination Certificate

active

06319851

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a packaging method of a semiconductor device having a plurality of bump electrodes, particularly, to a method of sealing bump electrodes formed on a substrate such as a silicon wafer.
FIGS. 13
to
17
collectively exemplify a method of manufacturing a semiconductor device called CSP (Chip Size Package). As shown in
FIG. 13
, a structure having a large number of bump electrodes
2
formed on a silicon substrate (semiconductor substrate)
1
of a wafer is disposed in a position-aligned state on an upper surface of a printing table
3
. Then, a printing mask
4
is disposed in a positioned-aligned state on the upper surface of the silicon substrate
1
. The printing mask
4
comprises a mask body
4
a
having a thickness slightly larger than the height of the bump electrode
2
. A circular open portion
4
b
slightly smaller than the planar size of the silicon substrate
1
is formed in the mask body
4
a.
In the next step, as shown in
FIG. 14
, a liquid sealing resin is printed on the surface of the substrate within the open portion
4
b
of the printing mask
4
with a squeegee
5
shaped like a strip so as to form a sealing film
6
. In this step, the upper surface of the bump electrodes
2
is covered with the sealing film
6
. Then, the upper surface of the sealing film
6
is grinded appropriately so as to expose the upper surface of the bump electrode
2
to the outside, as shown in FIG.
15
. Further, a solder ball
7
is formed on the upper surface of the bump electrode
2
, as shown in
FIG. 16
, followed by a dicing treatment so as to obtain individual semiconductor devices.
FIG. 17
is a cross sectional view showing a part of a semiconductor device
10
thus obtained, which is mounted to a circuit substrate
11
. In this case, the semiconductor device
10
is mounted to the circuit substrate
11
such that the solder ball
7
is bonded to a connection terminal
12
formed at a predetermined position on the surface of the circuit substrate
11
.
In the conventional semiconductor device
10
of the particular construction, the thickness of the sealing film
6
is equal to the height of the bump electrode
2
. As a result, each of the bump electrodes
2
is fixed to the sealing film
6
and, thus, is incapable of being deformed. As a result, in a temperature cycle test performed after the semiconductor device
10
is mounted to the circuit substrate
11
, the bump electrode
2
is incapable of absorbing the stress derived from the difference in the thermal expansion coefficient between the silicon substrate
1
and the circuit substrate
11
, giving rise to a problem that cracks are generated at the bump electrode
2
or the solder ball
7
.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of sealing bump electrodes capable of absorbing the stress acting on each of the bump electrodes and derived from the difference in thermal expansion coefficient.
According to one embodiment of the present invention, there is provided a method of sealing bump electrodes, comprising the steps of preparing a substrate having a number of bump electrodes formed apart from each other; mounting a mask having open portions each corresponding to at least a part of a region between the bump electrodes to the substrate; and forming a sealing film having a thickness smaller than the height of each of the bump electrodes on the mask by moving a squeegee onto the mask.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.


REFERENCES:
patent: 4627988 (1986-12-01), Spanjer
patent: 5147084 (1992-09-01), Behun et al.
patent: 5478700 (1995-12-01), Gaynes
patent: 5847456 (1998-12-01), Shoji
patent: 0 993 040 (2000-04-01), None
patent: 3-293740 (1991-12-01), None

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