Method for packaging integrated circuit chips

Details Method for packaging integrated circuit chips Method for packaging integrated circuit chips

2006-11-14

2006-11-14

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S774000, C257SE23011

Reexamination Certificate

active

07135779

ABSTRACT:
A method for packaging integrated circuits in a wafer format that eliminates wire bonds. A wafer substrate on which the integrated circuits have been fabricated is patterned and etched to form signal and ground via through the substrate. A back-side ground plane is deposited in contact with the ground vias. A protective layer is formed on the top surface of the substrate, and a protective layer is formed on the bottom surface of the substrate, where the bottom protective layer fills in removed substrate material between the integrated circuits. Vias are formed through the bottom protective layer, and the wafer substrate is diced between the integrated circuits.

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