Method for optimum erasing of EEPROM

Static information storage and retrieval – Read/write circuit – Erase

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365185, G11C 700

Patent

active

053696158

ABSTRACT:
Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM), An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses, Techniques include a 2-phase verification process interleaving between pulse applications; special handling of a sample of cells within each erasable unit group; defects handling; adaptive initial erasing voltages; and single- and hybrid-phase algorithms with sector to sector estimation of erase characteristics by table lookup. Techniques are also employed for controlling the uniformity of program/erase cycling of cells in each erasable unit group, Defects handling includes an adaptive data encoding scheme.

REFERENCES:
patent: 5070032 (1991-12-01), Yuan
patent: 5095344 (1992-03-01), Harari
patent: 5132935 (1992-07-01), Ashmore
patent: 5138580 (1992-08-01), Farrugia
patent: 5168465 (1992-12-01), Harari

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