Method for optimizing the structure of a transistor to withstand

Details Method for optimizing the structure of a transistor to withstand Method for optimizing the structure of a transistor to withstand

1993-03-04

1995-04-25

Arana, Louis

Electricity: measuring and testing

A material property using electrostatic phenomenon

For flaw detection

324719, 3241581, G01N 2760

Patent

active

054102545

ABSTRACT:
The present invention relates to a system and method of quantitatively evaluating the amount of electrostatic discharge that integrated circuit field effect transistors may endure before material damage results thereto. The system and method utilizes a plurality of test devices, each having certain differences in structure, which are fabricated onto a common integrated circuit substrate for contemporaneous testing of each device under controlled quantitative conditions. The test results may be organized into a "matrix experiment". A matrix experiment comprises a set of experiments where the settings or values of several product or process parameters to be studied are changed from one experiment to another. An orthogonal matrix array may be utilized to enhance the reliability of the data analysis, and may effectively reduce the number of experiments necessary to establish a reliable conclusion from the limited number of tests performed.

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Maloney et al, "Transmission Line Pulsing Techniques for Circuit Modeling of ESD Phenomena", EOS/ESD Symposium, Dec. 1985, pp. 49-54. (Intel Corporation).

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