Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-02-03
2001-03-13
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06202196
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for optimizing routing mesh segment width, which is used to maximize routing area for layers of integrated circuits and ensure that voltage drop and metal migration requirements are satisfied.
2. Description of the Related Art
Microelectronic integrated circuits comprise a large number of electronic components which are fabricated on a silicon base or wafer (chip). The design of an integrated circuit transforms a circuit description into a geometric description which is known as a layout. A layout consists of a set of planar geometric shapes in various layers of a silicon chip.
The process of converting electrical circuit specifications into a layout is called the physical design. Physical design involves placing predefined cells and elements in a fixed area, and routing wires between them. The process can be tedious, time consuming, and prone to many errors due to tight tolerance requirements and the minuteness of individual components. Current technology allows fabrication of several million transistors of less than one micron in size on one chip, and future developments are expected to allow fabrication of substantially more components of even smaller size.
Due to the large number of components and the exacting requirements of the fabrication process, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use Computer Aided Design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time, and enhanced chip performance. Routing is one phase of the physical design process which can benefit from automation.
Of the several layers fabricated in most integrated circuits, one or more layers typically is a power routing layer. Power routing layers can be thought of as a mesh which comprises horizontal and vertical segments, which are metal interconnections between a power source, ground, and the various cells or circuit elements of the integrated circuit. One problem is that there may be excessive voltage drops across some or all segments; if so, some transistors (typically at the chip's center) may receive insufficient gate voltage to operate properly. Another problem is with metal migration; prolonged continuous current through metal interconnections can cause them to break.
Routing mesh design must deal with these problems. First, the mesh segment widths must be such that the maximum voltage drop for the mesh is no more than a specified voltage drop requirement. Second, the mesh segment widths must be such that a metal migration requirement is met (this requirement is typically set to allow a minimum chip lifespan of around ten years without breaking of segments). Segment width must be designed to satisfy both the voltage drop and metal migration requirements. Due to the complexity of this problem, a design method suitable for automation is needed. Additionally, it is desirable to minimize the width, and thus area, of mesh segments so that the routing area of the layer is maximized.
Therefore, it is an object of this invention to provide a method for optimizing a routing mesh such that segment width is minimized while complying with a set of limitations such as voltage drop and metal migration requirements.
SUMMARY OF THE INVENTION
This object is achieved by the present invention, which comprises a method for optimizing routing mesh segment widths within limits imposed by voltage drop and metal migration requirements, beginning with an initial mesh comprising a plurality of horizontal segments forming rows and a plurality of vertical segments forming columns. The method comprises the following steps: First, a voltage drop and current density associated with each segment is determined. Then a first width for each segment is found by scaling each segment width using a voltage drop scaling factor so that the routing mesh has a maximum voltage drop that satisfies the voltage drop requirement.
Next, widths for each segment are determined such that the metal migration requirement minus a margin is satisfied. Then the method ensures that each segment within each row, and each segment within each column, is not more than a first scaling factor wider than its neighboring segments. A second width for each segment is found by ensuring that each segment within each row is not more than a second scaling factor wider than segments at a same vertical position in neighboring rows, and each segment within each column is not more than the second scaling factor wider than segments at a same horizontal position in neighboring columns. In alternative preferred versions, the step of finding a first width could follow the step of finding a second width, or could be performed in parallel with the step of finding a second width.
After the above steps have been performed, the method selects the larger of the first width and second width for each segment, determines the voltage drop and current density associated with each segment, and checks whether the voltage drop and metal migration requirements are violated. Finally, the above steps are repeated if the voltage drop or metal migration requirement is violated.
In a preferred version of the method of the present invention, the voltage drop scaling factor takes into account different voltage drop requirements for different megacells by being the maximum of an overall factor and different factors for different megacells.
With respect to the metal migration requirement, in a preferred version of the present invention, the first scaling factor is about 1.1, the second scaling factor is about 1.2, and it is assumed that current remains unchanged within each particular iteration.
These and other aspects, features, and advantages of the present invention will be apparent to those persons having ordinary skill in the art to which the present invention relates from the foregoing description and the accompanying drawings.
REFERENCES:
patent: 5349542 (1994-09-01), Brasen et al.
patent: 5404310 (1995-04-01), Mitsuhashi
patent: 5568395 (1996-10-01), Huang
Hsu Wen-Chuan
Huang Tammy
LSI Logic Corporation
Mitchell Silberberg & Knupp LLP
Siek Vuthe
Smith Matthew
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