Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2008-07-31
2011-12-20
Myers, Paul R (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C713S320000, C455S522000
Reexamination Certificate
active
08082380
ABSTRACT:
A transceiver that reduces power consumption when data is transferred between devices in different modes. The transceiver is arranged in a first node and in a second node, which communicate between each other. A first control unit generates a first signal transmitted from the first node in predetermined time intervals during a first period that establishes an environment for communication between the first node and the second node. The second node transmits a second signal transmitted in response to the first signal. The first control unit generates a third signal upon detection of the second signal. A second control unit gradually decreases amplitude of the first signal based on the third signal to set the amplitude of the first signal to a predetermined amplitude so that the second node is receivable of the first signal.
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Ogawa Hitoshi
Watanabe Hideaki
Fujitsu Semiconductor Limited
Myers Paul R
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