Method for optimizing a layout of supply lines

Details Method for optimizing a layout of supply lines Method for optimizing a layout of supply lines

2005-02-16

2008-11-18

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07454720

ABSTRACT:
A method for optimizing a circuit layout is provided which optimizes a circuit layout as a result of utilizing unused tracks of the circuit layout to expand supply lines. In a first step, a circuit layout is constructed by means of any circuit layout construction method, whereby requirements regarding the design of supply lines are reduced. Subsequently, in a second step, the method for optimizing a circuit layout is used.

REFERENCES:
patent: 5687108 (1997-11-01), Proebsting
patent: 6317353 (2001-11-01), Ikeda et al.
patent: 2001/0011362 (2001-08-01), Yoshinaga
patent: 2002/0024148 (2002-02-01), Itoh
patent: 2004/0107411 (2004-06-01), Saxena et al.
patent: 2006/0095872 (2006-05-01), McElvain et al.

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