Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-05-24
2004-05-11
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06735742
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a method for optimizing the cell layout and the cell arrangement on an integrated semiconductor.
In the creation of integrated circuits, circuit description languages are usually used, for example a high level language such as VHDL. A further possibility for circuit creation is to use a so-called schematic, a symbol-based item of information about the circuit, which can in turn be generated from a circuit description. Finally, it is also possible to design the circuit with the aid of a data path generator. The circuit described in this way must subsequently be converted into a layout which forms the basis of the graphical information which represents the components used for the integrated circuit on a semiconductor.
For this purpose, firstly a cell-based network list (CBN) is created. This is done with the aid of a synthesis program if a circuit description language such as VHDL or Verilog is used, and with the aid of an extraction program if a schematic is used.
The CBN is a hierarchically structured list of all the cells used for the circuit and the connections between the cells. A cell is understood to be a unit of functionally associated components or cells. This is because a cell can in turn be constructed from individual cells on account of the hierarchical structure of the CBN. During the creation of the CBN, the programs used access a so-called cell library which contains information about standard cells. In this case, a standard cell is a frequently used, very small unit of components with a defined function. An example of a standard cell may be an inverter formed from two transistors. Various items of information about the properties of the standard cells are stored in the standard cell library. These are grouped into so-called “views”, in accordance with their principal use with different representation and calculation programs. In this case, the layout view contains information about the structure of a cell in the two-dimensional extent of its components on the various exposure masks. This view in each case contains data for definition of the various polygons required for fabricating the cell. The schematics view describes the appearance of the cell in the circuit diagram of a schematic. The VHDL and Verilog views describe the cell in each of these programming languages. The timing view describes the temporal behavior of the cell when signals are applied to the inputs of the cell. The abstract view contains definitions with regard to the contour of the cell and the positions of the individual connections. During the concrete calculation of a screen, printer or exposure-device output of circuit data, the programs used access the cell library in order to use the information stored therein for calculating an output. As the bottommost hierarchical level, the standard cells provide the information about the appearance of the circuit in concretized form. Programs for processing VHDL programs also resort to the cell library in order to be able to process corresponding references in the VHDL program.
In addition to designators and connections, the CBN also contains references to said cell library, which are evaluated in later steps. A standard cell library contains many standard cells, for example an inverter, in various manifestations which differ in terms of their driver capability and thus also in terms of the size, number and arrangement of the components situated in the cell. The driver capability of a component or of its cell describes its ability to supply further components with voltage or current. The programs for generating the CBN are able to use indications in the circuit description or inherent knowledge about necessities of driver strengths or the like to select one of the various standard cells of a cell type and create a corresponding reference in the CBN to this standard cell.
A so-called layout is calculated in the next step. In this case, the methods used are differentiated into so-called “full custom” methods, in which the placement and dimensioning of the individual components are effected manually, and “semi custom” methods, in which the critical steps are carried out in an automated manner. The “semi custom” method, on which, moreover, the invention is based, will be described below. The layout is created by means of a program for placement and routing, i.e. the arrangement of the cells defined in the CBN next to one another and the connection of the terminal contacts of the cells in accordance with the specifications of the CBN. In this case, the programs used follow the hierarchical structure of the CBN and attempt to arrange in spatial proximity associated cells which, for example, are combined at a higher hierarchical level to form a larger cell. This arrangement is effected with the aid of information—obtained from the cell library—about the contour or the concrete layout of the respective cells to be placed (abstract or layout view). There are algorithms available for this purpose which generally attempt to minimize the overall area used and, at the same time, to optimize the connecting paths (interconnection) between the individual cells. The routing defines this electrical interconnection of the cells to one another and to the power supply lines. There are algorithms available for this purpose, too, which attempt to minimize the interconnect length used by the overall circuit. In order to attain this aim as far as possible, a customary method of arranging the cells consists in putting them into rows which have a respectively identical height, or into rows which all have the same height, in order, in this way, to enable the cells to be supplied with power in a continuous, linearly extending manner.
The result of the placement/routing is the layout, a database created in binary data and containing information about the arrangement of the cells of the planned circuit relative to one another using coordinates on an area, designators of the cells, references to cells of a lower hierarchical level or to standard cells from the cell library and information about the course of the interconnects to be arranged in the interconnection planes.
The layout is subsequently used for producing masks for exposure of the semiconductor.
In order, however, that the actual functional capability of the semiconductor that can be produced in this way can already be tested at the outset, and without major costs, various analysis and optimization tools have been developed.
In order to check the functional capability, generally a so-called simulator is initially used. For the purpose of simulation, a network list containing information about the electrical elements used in the layout is created from the layout by means of an extraction program. In terms of its syntax, this network list generally corresponds to the cell-based network list but is extended. The network list includes information about the arrangement and the appearance of the individual cells, but also contains further-reaching information, for example about the components used in the cells, expected capacitive coupling between two or more interconnects, and information about the influence on adjacent components. Thus, the network list created in this way is a more detailed version of the CBN which also incorporates information which is not actually available until after the creation of a concrete layout and thus the definition of the arrangement and connection of the cells to one another. The more information about the layout that is incorporated into the network list, the more precisely the subsequent simulation can be carried out. The simulation uses given physical and electrical laws to test whether the layout of the integrated circuit and the circuit itself correspond to the requirements. If the requirements are not met, the circuit can be changed by exchanging specific cells which, for example, have a higher driver capability. However, this presupposes the presence of such replacement cells with suitable dimensioning. Usually
Hatsch Joel
Kamp Winfried
Künemund Ronald
Lackerschmid Eva
Söldner Heinz
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Thompson A. M.
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