Method for optimising transistor performance in integrated...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C002S009000, C002S010000, C002S011000

Reexamination Certificate

active

11067200

ABSTRACT:
A method (300) for optimising transistor performance in semiconductor integrated circuits built from standard cells (12), or custom transistor level layout, is disclosed. An active area of NMOS diffusion is extended with a joining area (102) between two adjacent cells (112) having the same net on diffusion at the adjacent edges of each cell. The diffusion area is extended to limit the occurrence of active and nonactive interface to minimise lattice strain effects and improve transistor performance.

REFERENCES:
patent: 4700316 (1987-10-01), Nair
patent: 5701255 (1997-12-01), Fukui
patent: 6163877 (2000-12-01), Gupta
patent: 6393601 (2002-05-01), Tanaka et al.
patent: 6410972 (2002-06-01), Sei et al.
patent: 2002/0137307 (2002-09-01), Kim et al.
patent: 2003/0023935 (2003-01-01), McManus et al.
patent: 2003/0023937 (2003-01-01), McManus et al.
patent: 2004/0031004 (2004-02-01), Yoshioka
patent: 2004/0060030 (2004-03-01), Fujimoto
patent: 2004/0095797 (2004-05-01), Yuan et al.
patent: 2004/0143797 (2004-07-01), Nguyen et al.
patent: 2004/0168141 (2004-08-01), Wang et al.
patent: 2006/0003522 (2006-01-01), Lin et al.
Krishna B., et al: “Diffusion Sharing Across Cell Boundaries In Cell Based Design,” Circuits and Systems, 1996., IEEE 39th Midwest Symposium on Ames, IA, USA Aug. 18-21, 1996, New York, NY, USA, IEEE, US, vol. 1, Aug. 18, 1996, pp. 349-352.
Gupta A., et al: “Clip: An Optimizing Layout Generator for Two-Dimensional CMOS Cells,” Proceedings of the Design Automation Conference. Anaheim, Jun. 9-13, 1997, New York, ACM, US, vol. CONF. 34, Jun. 9, 1997, pp. 452-455.
Gupta A., et al: “Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells,” VLSI Design 1999. Proceedings. Twelfth International Conference on Goa, India Jan. 7-10, 1999, Los Alamitos, CA, USA, IEEE Comput. Soc, US, Jan. 7, 1999, pp. 453-459.

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