Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-09-04
2007-09-04
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C002S009000, C002S010000, C002S011000
Reexamination Certificate
active
11067200
ABSTRACT:
A method (300) for optimising transistor performance in semiconductor integrated circuits built from standard cells (12), or custom transistor level layout, is disclosed. An active area of NMOS diffusion is extended with a joining area (102) between two adjacent cells (112) having the same net on diffusion at the adjacent edges of each cell. The diffusion area is extended to limit the occurrence of active and nonactive interface to minimise lattice strain effects and improve transistor performance.
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Hughes Peter William
Monk Trevor Kenneth
Morton Shannon Vance
Dinh Paul
Icera Inc.
McDermott Will & Emery LLP
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