Method for operating an MFIS ferroelectric memory array

Details Method for operating an MFIS ferroelectric memory array Method for operating an MFIS ferroelectric memory array

2008-05-27

2008-05-27

Wilczewski, M. (Department: 2822)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C438S003000

Reexamination Certificate

active

07379320

ABSTRACT:
An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.

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