Method for operating an integrated circuit having a sleep mode

Details Method for operating an integrated circuit having a sleep mode Method for operating an integrated circuit having a sleep mode

1999-04-30

2002-05-07

Hoang, Huan (Department: 2185)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230030, C365S149000

Reexamination Certificate

active

06385113

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuits, and more specifically to integrated circuit memories.
BACKGROUND OF THE INVENTION
With each new generation of semiconductor memory, the size and power requirements of the memory array becomes more demanding. For example, when moving from a 4 Mb technology to a 16 Mb design, the array area must be increased in order to accommodate the additional memory cells. Increasing the array size, however, adversely effects certain electrical parameters required for optimal circuit performance.
In many applications, such as hand-held, battery powered devices, a low power mode is used to reduce the power consumption of the memory device. Sleep modes are desirable is such applications as they increase the battery life of the device. Sleep modes which provide finer granularity without. compromising data integrity are highly desirable. Additionally, as the memory array increases, it is inefficient to refresh an entire dynamic memory array where only a portion of the array will be used for an extended time period.
As the speed of these applications increases, it becomes more and more difficult to maintain the integrity of the memory cells as operation switches from normal operating to a low power operating mode and back. Most high density dynamic memory cells are dependent, sharing a plate reference voltage supplied by a nonideal source. Charge injected into a group of storage nodes may effect the quality and integrity of other storage nodes, causing malfunction.
Accordingly, a need exists for an efficient way to operate memory devices which reduces the power consumption of the memory.


REFERENCES:
patent: 5818777 (1998-10-01), Seyyedy
patent: 5901100 (1999-05-01), Taylor
patent: 6118719 (2000-09-01), Dell et al.
patent: 6199139 (2001-03-01), Katayama et al.

Affiliated with

Also associated with

Rating

Method for operating an integrated circuit having a sleep mode does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for operating an integrated circuit having a sleep mode, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for operating an integrated circuit having a sleep mode will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2871704