Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2002-09-19
2004-08-24
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S203000, C365S230060
Reexamination Certificate
active
06781889
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the semiconductor technology field. More specifically, the invention relates to a method of operating a semiconductor memory, in which data values are written to the memory cells of the semiconductor memory. The invention also relates to a semiconductor memory that is suitable for being operated by the method.
Semiconductor memories, in particular semiconductor memories having dynamic memory cells comprising a selection transistor and a storage capacitor, are constructed in a matrix-like manner. They comprise word lines running in one direction and bit lines running transversely with respect thereto. Memory cells are activated by activation of the word lines, and data values are read in and out via the bit lines and sense amplifiers connected thereto. A word line decoder selects at least one of the word lines for activation in dependence on a word line address. A bit line decoder selects the bit line to be read, so that a memory cell arranged at a crossover between word line and bit line can be individually addressed.
For testing the semiconductor memory, data values representing a predetermined test pattern are written to the semiconductor memory. Afterward, the written-in data are read out again and compared with the written-in value by the test system. If a deviation is ascertained, a functional error is present, for example within the memory cell, the word line, the bit line or the corresponding decoders or even at some other location. In order to be able to test all of the memory cells sufficiently thoroughly according to different criteria, it is necessary for the memory cell array to be written to and read from a number of times. Given the multiplicity of memory cells in present-day semiconductor memories, by way of example semiconductor memories with 256 Mbit dynamic memory cells are available nowadays, just the process of writing to and reading from the memory cells takes up a not inconsiderable time. In order to reduce the test time, endeavors are made to carry out the process of writing predetermined data values to the memory cells as quickly as possible.
Semiconductor memories nowadays have a burst mode. This means that after the application of a start address, a number of memory cells prescribed by the burst length is automatically read. In the case of a cell array with n word lines and m addresses for the selection of bit lines, a number of n*m/burst length write accesses are necessary in order to write to the cell array in its entirety. The duration for writing to the semiconductor memory is therefore essentially determined by the memory size n*m.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor memory and a method of operating a semiconductor memory which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which allows the memory cells to be written to as quickly as possible. A further object of the invention is to specify a semiconductor memory which is particularly suitable for carrying out the method.
With the foregoing and other objects in view there is provided, in accordance with the invention, a novel method of operating a semiconductor memory, wherein the semiconductor memory comprises:
a memory cell array having memory cells for selectively storing a first logic value and a second logic value, word lines and bit lines, each of the memory cells being connected to one of the word lines and one of the bit lines;
a decoder for simultaneously selecting of one or a plurality of the word lines;
a voltage generator connected to the bit lines, for applying a predetermined voltage level to the bit lines;
and the method includes the steps of:
carrying out a potential equalization of in each case two bit lines;
subsequently bringing the bit lines to a level representing the first logic value or the second logic value; and
subsequently selecting a multiplicity of the word lines and writing the levels applied to the bit lines to the memory cells connected to the selected word lines.
In other words, he invention proposes a method for operating a semiconductor memory, the semiconductor memory comprising: a memory cell array having memory cells in order to store a first or a second logic value, having word lines and bit lines, each of the memory cells being connected to one of the word lines and one of the bit lines, a decoder for the simultaneous selection of one or a plurality of the word lines, a voltage generator, to which the bit lines are connected in order to apply a predetermined level to the bit lines, and the method comprising the following steps: a potential equalization of in each case two bit lines is carried out, after the conclusion of the potential equalization, the bit lines are brought to a level representing the first or the second logic value, afterward, a multiplicity of the word lines is selected and the levels applied to the bit lines are written to the memory cells connected to the selected word lines.
With the above and other objects in view there is also provided, in accordance with the invention, a semiconductor memory that comprises: a memory cell array having memory cells in order to store a first or a second logic value, having word lines and bit lines, each of the memory cells being connected to one of the word lines and one of the bit lines, a decoder for the simultaneous selection of one or a plurality of the word lines, a voltage generator in order to apply a predetermined level to the bit lines, the voltage generator being designed to generate, on the output side, a level representing the first logic value, a level representing the second logic value, or an equalization level lying between these levels.
The invention is particularly suitable for preallocating a constant logic value, for example “0” or “1”, to the entire memory cell array or at least selected portions of the memory cell array. For this purpose, after the application of the equalization level VBLEQ that biases the bit lines, via the same circuit path, either the level representing the logic “0” or the level representing the logic “1” is applied to the bit lines. The word lines are activated, so that the storage capacitor is connected to the respective bit lines. The levels applied to the bit lines are then written to the memory cells. All the word lines connected to the respective word line decoder can be activated, so that, in this way, a logic “0” or alternatively a logic “1” is written to the entire memory cell array including all the memory cells. Since the data values are not written to the memory cells via the conventional read-in path, but rather by additional circuit measures, this operation is designated as physical writing-in of a “0” or “1”.
It is also possible for only one portion of the word lines connected to the word line decoder to be activated, so that the respective data values are written only to those memory cells which are connected to this portion of the word lines. In an advantageous manner, “0”, for example, may be written to the memory cells which are connected to said first portion of the word lines, while by contrast the opposite data value, for example “1”, may be written to the memory cells which are connected to the other, complementary portion of the word lines. In an expedient manner, a logic “0” is written to the memory cells connected to one of the word lines, while a logic “1” is written to the memory cells connected to the directly adjacent word line. This principle is continued such that a logic “0” is again written to the memory cells of the next word line in turn arranged directly adjacent. In this way, it is possible for the memory cell array to be preallocated the data values “0” and “1” in a stripwise manner. If the strip-type writing-in is considered as described above, then there are situated between the memory cells of two word lines which are preallocated one of the data values the memory-cells of a further word line which are preallocated the co
Kliewer Jörg
Lukas Rupert
Pröll Manfred
Schröder Stephan
Greenberg Laurence A.
Infineon - Technologies AG
Lam David
Mayback Gregory L.
Stemer Werner H.
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