Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Testing or evaluating
Reexamination Certificate
2007-09-05
2011-11-15
Garbowski, Leigh (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Testing or evaluating
C716S139000
Reexamination Certificate
active
08060851
ABSTRACT:
A method for operating a secure semiconductor IP access server to support failure analysis. A client presents a test failure and failure type to an automated server which traverses an electronic product design, definition, and test database to report specifically those components and interconnect likely to cause the failure with geometrical information which may be displayed on the client. Other aspects of semiconductor IP are protected by the server by limiting the trace mechanism and renaming components.
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Chan Gerald S.
Crouch Alfred L
Dokken Richard C.
Orbon Jacob J
Garbowski Leigh
Holland & Hart LLP
Verigy (Singapore Pte. Ltd.
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