Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2002-06-04
2002-12-03
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185180, C257S316000, C257S317000
Reexamination Certificate
active
06490196
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method for operating a non-volatile memory, and more particularly, to a method of programming, reading, and erasing a flash memory having embedded word lines.
2. Description of the Prior Art
Flash memories have the property of being electrically programmable and erasable, and because of their usefulness, they are widely applied in electronic products such as portable computers and communication equipment. In general, flash memory cells can be divided into two types: a stacked gate type and a split gate type, according to the structure of their gates.
Flash memory cells of both stacked gate type and split gate type are arranged in an array, and each memory cell usually stores one bit of information. In each memory cell, a source and a drain are formed in an n-type or a p-type silicon substrate. A tunneling dielectric layer is formed between the source and the drain. A floating gate and a controlling gate, separated by an insulating layer, are formed on the tunneling dielectric layer. The floating gate is used for storing an electrical charge and the controlling gate is used to control the accessing and storing of information. Additionally, memory cells are isolated from one another by field oxide layers or shallow trench isolation. In order to enhance the efficiency of the programming and erasing of flash memories, a memory cell with a larger area for the purpose of obtaining a high coupling ratio is required. However, a memory cell with too large of an area is difficult to integrate with other components.
Thus, the memory cell disclosed in U.S. Pat. No. 6,011,725 attempts to solve the above-mentioned problem. The memory cell uses an electrically erasable programmable ROM (EEPROM) as an example. As shown in
FIG. 1
, in a memory cell with two binary bits of information, a source
12
and a drain
14
are formed in a semiconductor substrate
10
. A channel
16
is positioned in the semiconductor substrate
10
between the source
12
and the drain
14
. A silicon oxide layer
18
, a trapping layer
20
(such as silicon nitride), and a silicon oxide layer
22
are sequentially formed on the semiconductor substrate
10
. A gate
24
is positioned on the silicon oxide layer
22
. The memory cell is programmed by hot electron injection. Using the right bit as an example, when grounding the source
12
and applying a voltage on the gate
24
and the drain
14
, electrons are sped up and gain sufficient energy to inject into a region of the trapping layer
20
close to the drain
14
. When reading the right bit, a large enough voltage is applied to the gate
24
and the source
12
. That is, reading and programming are performed in opposite directions for each bit in the memory cell.
The above-mentioned flash memory has an advantage that each memory cell stores two bits of information. However, reading and programming are performed in opposite directions for each bit. That is, as shown in
FIG. 1
, when reading the right bit, the drain
14
serves as a source terminal and the source
12
serves as a drain terminal. When reading the left bit, the drain
14
serves as a drain terminal and the source
12
serves as a source terminal. The read method accomplished by alternating the source and the drain increases the complexity and the total area of periphery circuits. That is, the above-mentioned flash memory enhances the integration of the memory cells, however, it also increases the total area of periphery circuits.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide a method of programming, reading, and erasing a flash memory having embedded word lines and a sandwich structure comprising a first oxide layer, a trapping layer and a second oxide layer. The flash memory will not alternate the source and the diffusion drain when reading the left bit and the right bit of a flash memory cell.
It is another objective of the claimed invention that the embedded gate structure utilized in the claimed invention effectively reduces the total area of the memory cells and simplifies the periphery circuits. Thus, the memory cell capable of storing two bits of information in the claimed invention satisfies requirements for high density memories.
According to the claimed invention, the flash memory cell comprises an N-type well implanted in a substrate. A P-type well and an embedded gate structure are alternatively arranged on the N-type well. An N-type doped region, serving as a source terminal, is positioned beneath the embedded gate structure. A diffusion drain is positioned on the P-type well and a conductive layer connects with the diffusion drains. The embedded gate structure comprises a gate, a first oxide layer, a trapping layer, and a second oxide layer, wherein the gate is surrounded by the first oxide layer, the trapping layer, and the second oxide layer. In addition, an insulating layer is formed on the embedded gate structure. A left bit and a right bit are formed in the trapping layer of the left and right sides of the embedded gate structure. The above-mentioned structure of the memory cell is used to perform the reading, programming, and erasing operation of the left bit and the right bit.
It is an advantage against the prior art that complexity and total areas of periphery circuits are effectively reduced. In addition, an array of many two bit flash memory cells of the claimed invention does not require field oxide layers or shallow trench isolation. Furthermore, the claimed invention has the advantages of simple fabrication, high density, and small area.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the multiple figures and drawings.
REFERENCES:
patent: 5016068 (1991-05-01), Mori
patent: 5990509 (1999-11-01), Burns et al.
patent: 6130453 (2000-10-01), Mei et al.
patent: 6143636 (2000-11-01), Forbes et al.
patent: 6204123 (2001-03-01), Mori
Hsu Ching-Hsiang
Lee Kung-Hong
Yang Ching-Sung
e-Memory Technology, Inc.
Hsu Winston
Mai Son
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