Static information storage and retrieval – Systems using particular element – Semiconductive
Reexamination Certificate
2001-08-22
2002-08-27
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Semiconductive
C365S174000
Reexamination Certificate
active
06442065
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the field of integrated circuits. The invention relates to a method for operating a memory cell configuration having dynamic gain memory cells.
At present, a so-called one-transistor memory cell is usually used as a memory cell of a memory cell configuration. Such a memory cell includes a transistor and a capacitor on which information is stored in the form of a charge. By driving the transistor through a word line, it is possible for the charge on the capacitor to be read out through a bit line. Because the charge of the capacitor drives the bit line and a signal generated by the charge is intended to remain identifiable despite background noise, the capacitor must have a minimum capacitance. The minimum capacitance requirement placed on the capacitor constitutes an obstacle to increasing the packing density of the memory cell configuration because the size of the capacitor cannot be arbitrarily reduced.
The problem is avoided in an alternative memory cell configuration in which so-called gain cells, i.e., dynamic gain memory cells, are used as memory cells. In such a configuration, too, the information is stored in the form of an electrical charge. However, the electrical charge does not have to directly drive a bit line. Rather, it is stored on a gate electrode of a memory transistor and serves only for controlling the latter, for which purpose a very small quantity of electrical charge is already sufficient.
European Patent Application 537203, corresponding to U.S. Pat. No. 5,327,374 to Krautschneider et al., describes a memory cell configuration in which a memory cell is a dynamic gain memory cell including a selection transistor, a memory transistor, and a Shottky junction. A gate electrode of the selection transistor is connected to a word line. The selection transistor and the memory transistor are connected in series and between a bit line and a voltage terminal at which an operating voltage is present. The Shottky junction is connected between the gate electrode of the memory transistor and a source/drain region of the selection transistor. To write information to a memory cell, the associated word line drives the associated selection transistor. Depending on the type of information, a low voltage U
BL
or a high voltage U
BH
is applied to the bit line. The charge on the gate electrode of the memory transistor that is established in the process is dependent on the voltage on the bit line and represents the information. To read out the information, the selection transistor is driven through the word line and the low voltage U
BL
is applied to the bit line. If the gate electrode of the memory transistor was previously charged by the high voltage U
BH
on the bit line, then a voltage difference between the gate electrode and a source/drain region of the memory transistor arises that is greater than a threshold voltage of the memory transistor, with the result that a signal charge is brought about by a current between the voltage terminal and the bit line. If the gate electrode of the memory transistor was charged by the low voltage U
BL
on the bit line, then no voltage difference between the gate electrode and the source/drain region of the memory transistor arises that is greater than the threshold voltage of the memory transistor, resulting in no current flow.
The article by M. Heshami et al., “A 250-MHz Skewed-Clock Pipelined Data Buffer,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 3 (1996) 376, describes a memory cell configuration in which a memory cell is a dynamic gain memory cell that includes a first selection transistor, a memory transistor, and a second selection transistor. The first selection transistor is connected between a first bit line and a gate electrode of the memory transistor. A gate electrode of the first selection transistor is connected to a first word line. The second selection transistor is connected between a source/drain region of the memory transistor and a second bit line. A gate electrode of the second selection transistor is connected to a second word line. A further source/drain region of the memory transistor is connected to a voltage terminal. To write an information item to the gate electrode of the memory transistor, the first selection transistor is driven through the first word line, resulting in the establishment, on the gate electrode of the memory transistor, of a voltage that is dependent on a voltage on the first bit line, the magnitude of which, in turn, depends on the information to be written. To read out the information, the second selection transistor is driven through the second word line. Depending on the information, i.e., depending on the voltage on the gate electrode of the memory transistor, the memory transistor is in the on state or in the off state, and a current does or does not flow between the voltage terminal and the second bit line.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for operating a memory cell configuration having dynamic gain memory cells that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and, in which, for a given operating voltage, a signal charge is greater than in comparison with the prior art.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for operating a memory cell configuration having dynamic gain memory cells including the steps of providing memory cells each having at least one memory transistor with a gate electrode and first and second drain/source regions, writing a first information item to a memory cell by charging a gate electrode of a memory transistor of the memory cell with a first voltage, writing a second information item to the memory cell by charging the gate electrode of the memory transistor with a second voltage, respectively reading out the first information item and the second information item by applying an operating voltage to a first source/drain region of the memory transistor and applying a read-out voltage to a second source/drain region of the memory transistor, setting the first voltage to lie between the second voltage and the readout voltage, setting the read-out voltage to lie between the first voltage minus a threshold voltage of the memory transistor and the second voltage minus the threshold voltage of the memory transistor, and selecting the operating voltage such that the memory transistor is in an off state when the first information item is read out.
Providing a signal charge is greater than in comparison with the prior art can be achieved with a method for operating a memory cell configuration having dynamic gain memory cells, in which the memory cells each include at least one memory transistor. To write a first information item to one of the memory cells, a gate electrode of the associated memory transistor is charged such that a first voltage is present on it. To write a second information item to the memory cell, the gate electrode of the memory transistor is charged such that a second voltage is present on it. In each case, in order to read out the first information item and to read out the second information item, an operating voltage is applied to a first source/drain region of the memory transistor, and a read-out voltage is applied to a second source/drain region of the memory transistor. The first voltage lies between the second voltage and the read-out voltage. The read-out voltage lies between the first voltage minus a threshold voltage of the memory transistor and the second voltage minus the threshold voltage of the memory transistor.
The dynamic gain memory cell includes the memory transistor, on whose gate electrode the information is stored in the form of a charge. During writing, the charge is set such that, in the case of the first information item, the memory transistor is in the off state, i.e., no current can flow through the memory transistor, whereas it is in the on sta
Hofmann Franz
Krautschneider Wolfgang
Schlösser Till
Willer Josef
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Nguyen Tan T.
Stemer Werner H.
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