Method for offsetting a silicide process from a gate...

Details Method for offsetting a silicide process from a gate... Method for offsetting a silicide process from a gate...

2007-02-20

2007-02-20

Norton, Nadine (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S706000, C438S745000

Reexamination Certificate

active

10860100

ABSTRACT:
A method for offsetting silicide on a semiconductor device having a polysilicon gate electrode, source and drain regions in a substrate, and source and drain extensions in the substrate, employs a titanium nitride sidewall spacer on the sidewalls of the polysilicon gate electrode. The titanium nitride sidewall spacer prevents silicide growth on top of the source and drain extensions during a salicidation process. The titanium nitride sidewall spacers are then removed by an etching process that does not etch the silicide regions formed in the source and drain regions and the polysilicon gate electrode. Following removal of the titanium nitride sidewall spacers, a low k interlevel dielectric layer or a stress liner may be deposited on top of the devices to enhance device performance.

REFERENCES:
patent: 6121139 (2000-09-01), Chang et al.
patent: 6136705 (2000-10-01), Blair
patent: 6255227 (2001-07-01), Donaton et al.
patent: 6329695 (2001-12-01), Duane et al.

Affiliated with

Also associated with

Rating

Method for offsetting a silicide process from a gate... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for offsetting a silicide process from a gate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for offsetting a silicide process from a gate... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3825088