Method for novel SOI DRAM BICMOS NPN

Details Method for novel SOI DRAM BICMOS NPN Method for novel SOI DRAM BICMOS NPN

2000-09-07

2002-12-10

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S234000, C257S349000

Reexamination Certificate

active

06492211

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor devices and, more particularly, to a structure and method for novel silicon on oxide structure having both bipolar and CMOS devices.
BACKGROUND OF THE INVENTION
Integrated semiconductor circuits, particularly memory circuits employing cells which include a storage capacitor and a single switch, such as dynamic random access memories (DRAM), have achieved high memory cell densities. These cells employ a storage capacitor and a field effect transistor (FET) acting as a switch to selectively connect the capacitor to a bit/sense line.
Silicon on insulator (SOI) in semiconductor devices provides a high performance regime for CMOS operation due to its unique isolation structure. Advantageously, a complementary pair of bipolar devices within the CMOS framework are integrated for low voltage, high performance operation. Such integration is referred to a BICMOS technology. Advantageously, the BICMOS technology will make use of as much of the CMOS advantages as possible.
The present invention is directed to further improvements in BICMOS technology and to improvements in dynamic drive sense amplifiers.
SUMMARY OF THE INVENTION
In accordance with-the invention, a unique fabrication sequence is provided and the structure of a vertical silicon on insulator (SOI) bipolar transistor integrated into a typical DRAM trench process sequence. A DRAM array utilizing an NFET allows for an integrated bipolar NPN sequence. Similarly, a vertical bipolar PNP device is implemented by changing the array transistor to a PFET.
In accordance with another aspect of the invention, a dynamic drive sense amplifier is enabled by the novel structure. This novel dynamic drive sense amplifier provides a solution for sensing low level signals in a low voltage environment.
In one aspect of the invention there is disclosed a BICMOS device fabricated in SOI. The bipolar emitter contacts and CMOS diffusion contacts are formed simultaneously of polysilicon plugs. The CMOS diffusion contact is the plug contact from bitline to storage node of a memory cell.
There is disclosed in accordance with another aspect of the invention a circuit for a dynamic drive sense amplifier. The circuit includes a preamplifier using NPN transistors cross-coupled with NMOS switches. A CMOS latch is connected in parallel controlled by separate control signals and operated in a second bitline drive phase. The preamplifier is biased by a displacement current from a MOS capacitor.
Further features and advantages of the invention will be readily apparent from the specification and from the drawings.


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