Method for non-volatile memory with reduced erase/write...

Details Method for non-volatile memory with reduced erase/write... Method for non-volatile memory with reduced erase/write...

2006-09-12

2009-10-20

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S185030, C365S185190, C365S185330, C365S238500

Reexamination Certificate

active

07606091

ABSTRACT:
High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested in successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.

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