Method for non-intrusive cache fills and handling of load misses

Details Method for non-intrusive cache fills and handling of load misses Method for non-intrusive cache fills and handling of load misses

1997-06-25

2000-04-18

Eng, David Y.

Electrical computers and digital processing systems: processing

Instruction issuing

Simultaneous issuance of multiple instructions

G06F 928

Patent

active

060527757

ABSTRACT:
A method for operating a processor that executes coded instructions using an instruction scheduling unit receiving the coded instructions and issuing an instruction for execution. A replay signaling device generates a signal indicating when the instruction failed to execute properly within a predetermined time. A replay device within the instruction scheduling unit responsive to the signaling device then reissues the instruction for execution.

REFERENCES:
patent: 5651125 (1997-07-01), Witt et al.
patent: 5828860 (1998-10-01), Miyaoku et al.
patent: 5832249 (1998-11-01), Tran et al.
patent: 5835946 (1998-11-01), Allen et al.
Smith, Alan Jay; "Cache Memories," Computing Surveys, vol. 14, No. 3, Sep. 1982, pp. 473-530.

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