Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2002-07-02
2004-10-12
Phung, Anh (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S065000
Reexamination Certificate
active
06804139
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns a method for determining a logic state of a memory cell in a data storage device, wherein said cell stores data in the form of an electrical polarization state in a capacitor containing a polarizable material, wherein said polarizable material is capable of maintaining a non-vanishing electrical polarization in the absence of an externally impressed voltage across said capacitor, and of generating a current response to an applied voltage, said current response comprising linear and non-linear components. The present invention also concerns a first apparatus for performing a phase comparison in a method according to the invention wherein the apparatus comprises a signal generator for supplying a read signal with given frequency to a memory cell, wherein the memory cell in response to the read signal outputs a response component at twice the given phase of the read signal; as well as a second apparatus for performing a phase comparison in the method according to the invention, wherein the apparatus comprises a signal generator for supplying two or more read signals with given phases to a memory cell, wherein the memory cell in response to said read signals outputs a response signal having two or more non-linear current components.
Particularly the present invention concerns a non-destructive readout of memory cells, wherein the polarizable material exhibits hysteresis, notably an electret or a ferroelectric material, as known in the art.
2. Description of Related Art
During recent years, data storage has been demonstrated in electrically polarizable media consisting of thin films of ceramic or polymeric ferroelectrics. A major advantage of such materials is that they retain their polarization without the permanent supply of electrical energy, i.e. the data storage is non-volatile.
Two main classes of memory devices have been demonstrated where the logic state of an individual memory cell is represented by the polarization direction of the ferroelectric thin film in that cell. In both cases data are written into the memory cells by polarizing the film in the desired direction through the application of an appropriately directed electrical field exceeding the coercive field of the ferroelectric. However, device architectures are fundamentally different:
In the first class of devices, each memory cell incorporates at least one transistor. The overall memory architecture is of the active matrix type, the major advantage compared with traditional SRAM and DRAM devices being the non-volatile nature of the ferroelectrically stored logic state.
One broad sub-class of such ferroelectric-based memory devices, commonly termed FeRAM or FRAM (a Symetrix copyrighted term), is extensively described in the scientific and patent literature and is presently being commercialized by a number of companies worldwide. In its simplest form (1T-1C architecture), each FeRAM memory cell has a single transistor and capacitor as illustrated in
FIG. 1
, where the capacitor contains a ferroelectric which can be polarized in one or the other direction, representing a logic “0” or “1”, respectively. A given memory cell is written, i.e. prepared with the ferroelectric capacitor polarized in the desired direction, by applying appropriate voltages to the wordline, bitline and driveline serving that cell. Reading is performed by floating the bitline and applying a positive voltage to the driveline while asserting the wordline. Depending on the direction of polarization in the capacitor, i.e. whether the cell stores a logic “0” or a “1”, the charge transferred to the bitline in this process shall be either significant or small, and the logic state of the cell is determined by recording the magnitude of this charge. Since this read operation is destructive, the data must be written back afterwards to avoid permanent loss of stored information. A large number of patents have been issued on variants of the basic FeRAM concept, see, e.g. U.S. Pat. No. 4,873,664 (Ramtron International Corp.), U.S. Pat. No. 5,539,279 (Hitachi, Ltd), U.S. Pat. No. 5,530,668 (Ramtron International Corp), U.S. Pat. No. 5,541,872 (Micron Technology), U.S. Pat. No. 5,550,770 (Hitachi, Ltd), U.S. Pat. No. 5,572,459 (Ramtron International Corp), U.S. Pat. No. 5,600,587 (NEC Corp.), U.S. Pat. No. 5,883,828 (Symetrix Corp.). The patents address both circuit architectures and materials, reflecting difficult problems that have hindered practical implementation of ferroelectric memories since their conceptual introduction decades ago. Thus, the destructive read aspect of these memories has comported fatigue in the ferroelectric materials used, limiting the operational lifetime and thus basic usability for large classes of applications. Following intensive efforts, certain materials (e.g. PZT and SBT) have been refined and modified so as to sustain the large number of switching cycles (10 exp 10 to 10 exp 14) of relevance in the most demanding applications, as well as exhibiting adequate resistance to imprint, etc. However, these optimized materials require annealing at high temperatures, are vulnerable to hydrogen exposure, etc, and generally pose costly and complex problems in connection with integration into high volume production based on established silicon device manufacturing. Further, their requirement for thermal treatment makes them unsuitable for future integration in polymer-based electronic devices. Some of the patents reflect efforts to circumvent drift and manufacturing tolerance problems by making use of more complex architectures. This may include memory cells containing two ferroelectric capacitors and two transistors (2C-2T designs) to allow for referencing cells and circuits and more complex pulsing protocols. It may be noted that at present all ferroelectric memories in production use the 2C-2T architecture, since materials are still lacking that have adequate stability under exposure to time, temperature and voltage cycling (cf.: D. Hadnagy: “Making ferroelectric memories”, The Industrial Physicist, pp.26-28 (December 1999)).
In another subclass of devices employing one or more transistors in each memory cell, the source-drain resistance of a transistor in the cell is directly or indirectly controlled by the polarization state in a ferroelectric capacitor in that cell. The basic idea is not new and has been described in the literature (cf., e.g. Noriyoshi Yamauchi, “A metal-Insulator-Semiconductor (MIS) device using a ferroelectric polymer-thin film in the gate insulator”, Jap.J.Appl.Phys. 25, 590-594 (1986); Jun Yu et al., “Formation and characteristics of Pb(Zr,Ti)O
3
buffer layer”, Appl.Phys.Lett. 70, 490-492 (1997); Si-Bei Xiong and Shigeki Sakai “Memory properties of SrBi
2
Ta
2
O
9
thin films prepared on SiO
2
/Si substrates”, Appl.Phys.Lett. 70, 1613-1615 (1999)). In U.S. Pat. No. 5,592,409 (Rohlm Co., Ltd.), Nishimura et al. describe a non-volatile memory based on a ferroelectric film which is polarized in one or the other direction, representing a logic “0” or “1”. The polarized ferroelectric provides bias on the gate of a transistor, thereby controlling the current flow through the transistor. An obvious advantage of this mode of operation is that the logic state of the memory cell can be read non-destructively, i.e. without incurring polarization reversal in the ferroelectric capacitor. A related concept, described by J. T. Evans and J. A. Bullington in U.S. Pat. No. 5,070,385, is based on a semiconductor material in close contact with the ferroelectric. Here, the semiconducting material exhibits an electrical resistance which depends on the state of polarization in the ferroelectric. Unfortunately, there remain severe unsolved materials—and processing issues in connection with all of the above mentioned concepts (cf., e.g. D. Hadnagy, “Making ferroelectric memories”, The Industrial Physicist, pp.26-28 (December 1999)), and their successful commercialization in the foreseeable future is at present doubtful.
In both subclasses refer
Phung Anh
Thin Film Electronics ASA
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