Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-30
2007-10-30
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S016000
Reexamination Certificate
active
11129786
ABSTRACT:
A circuit design method utilizes existing late mode worst case slack calculation functions inherent in timing path trace algorithms which only need to record the worst arrival and worst required arrival times at each netlist node as traced paths. Because of this, most individual path tracing is curtailed due to the likelihood that a more critical arrival or required arrival time has already been recorded at a given netlist node. Worst case slacks are then determined by subtracting the worst case arrival time from the worst case required arrival time. In this manner, worst case slack values are calculated for the entire netlist within a reasonable amount of time. The method uses these existing functions by querying the worst case slack at each netlist node under varied timing model scenarios. These varied timing model scenarios include altering the cell and net delays and arrival times in the model. Then, with the worst case slacks from the varied timing model scenarios in hand, the required priority factors, recoverability and path composition factors are computed by comparing the differences in the worst case slack at each netlist node.
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Curtin James J.
McIlvain Kevin M.
Raphy Ray
Search Douglas S.
Szulewski Stephen
Augspurger Lynn L.
Kik Phallaka
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