Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Patent
1997-01-10
1999-07-13
Lee, Thomas C.
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
710 55, 710 56, 711147, 711154, 709234, G06F 1300
Patent
active
059220570
ABSTRACT:
In a multiprocessor data processing system including at least one main processor and one sub-processor utilizing a shared queue, queue integrity is maintained by associating a semaphore with each queue entry to indicate ownership of that queue entry. Ownership of a queue entry is checked by a processor attempting to post to the queue entry. Upon determining that the queue entry is available to the processor, the queue entry is loaded by an atomic write operation, ownership of the queue entry transferred to another processor, and the other processor may be alerted of the post to the queue. The other processor maintains ownership of the queue entry until the other processor has read and saved the data from the queue entry. Items may thus be posted to the queue and cleared from the queue by a processor independent of the state of the other processor. No locking mechanism or atomic read-modify-write capability is required to enforce mutual exclusion between the main processor and the sub-processor to maintain queue integrity.
REFERENCES:
patent: 4038642 (1977-07-01), Bouknecht et al.
patent: 4429360 (1984-01-01), Hoffman et al.
patent: 4663706 (1987-05-01), Allen et al.
patent: 4807111 (1989-02-01), Cohen et al.
patent: 4821170 (1989-04-01), Bernick et al.
patent: 4945548 (1990-07-01), Iannarone et al.
patent: 5003464 (1991-03-01), Ely et al.
patent: 5023776 (1991-06-01), Gregor
patent: 5224215 (1993-06-01), Disbrow
patent: 5239634 (1993-08-01), Buch et al.
patent: 5274823 (1993-12-01), Brenner et al.
patent: 5313587 (1994-05-01), Patel et al.
patent: 5313638 (1994-05-01), Ogle et al.
patent: 5315707 (1994-05-01), Seaman et al.
patent: 5319778 (1994-06-01), Catino
patent: 5325526 (1994-06-01), Cameron et al.
patent: 5341491 (1994-08-01), Ramanujan
patent: 5363497 (1994-11-01), Baker et al.
patent: 5381413 (1995-01-01), Tobagi et al.
patent: 5386514 (1995-01-01), Lary et al.
patent: 5388215 (1995-02-01), Baker et al.
patent: 5394547 (1995-02-01), Correnti et al.
patent: 5404521 (1995-04-01), Murray
patent: 5442730 (1995-08-01), Bigus
patent: 5519883 (1996-05-01), White et al.
patent: 5539893 (1996-07-01), Thompson et al.
patent: 5541912 (1996-07-01), Choudhury et al.
patent: 5546391 (1996-08-01), Hochschild et al.
patent: 5551001 (1996-08-01), Cohen et al.
patent: 5555396 (1996-09-01), Alferness et al.
patent: 5555405 (1996-09-01), Griesmer et al.
patent: 5560034 (1996-09-01), Goldstein
patent: 5579504 (1996-11-01), Callander et al.
patent: 5581734 (1996-12-01), DiBrino et al.
patent: 5604866 (1997-02-01), Kolb et al.
patent: 5623449 (1997-04-01), Fischer et al.
patent: 5740467 (1998-04-01), Chmielecki, Jr. et al.
patent: 5774745 (1998-06-01), Ecclesine
Bailey Wayne P.
Lee Thomas C.
LSI Logic Corporation
Wang Albert
Yee Duke W.
LandOfFree
Method for multiprocessor system of controlling a dynamically ex does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for multiprocessor system of controlling a dynamically ex, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for multiprocessor system of controlling a dynamically ex will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2271916