Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1996-12-23
2000-03-07
Chan, Eddie P.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
711117, G06F 1100
Patent
active
060354119
ABSTRACT:
The present invention is a method and apparatus for organizing memory buffers between an i/o subsystem and a computer system. The present invention organizes the memory buffers that exist between a computer system and an associated i/o subsystem into a memory hierarchy. An example of such a hierarchy includes, in order, a disk buffer, a disk cache, a controller memory and a computer system memory. Each datablock in the memory hierarchy is given an associated index word. The index word contains the address of the datablock within the media of the disk drive and contains index bits which indicate where the datablock may be found in the memory hierarchy. As a datablock moves between the disk drive and the computer system, a mirror copy of the datablock is maintained in a memory buffer that is in the next adjacent level of the memory hierarchy. In this way, the mirror copy may be used if the datablock becomes inaccessible.
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Chan Eddie P.
Hitachi Computer Products, Inc.
Portka Gary J.
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