Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2008-06-24
2008-06-24
Luu, Pho M. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S185020, C365S185260, C365S185280
Reexamination Certificate
active
07391659
ABSTRACT:
A memory cell is programmed by injecting charge into a charge storage layer of the memory cell. A desired programmed charge results in the charge storage layer over an edge portion of a channel region of the memory cell. An undesired programmed charge results in the charge storage layer over an inner portion of the channel region. Charge tunneling is used to substantially remove the undesired programmed charge in the charge storage layer. In one form the memory cell has a substrate having a channel region, a first dielectric layer over the substrate and a charge storage layer over the first dielectric layer. A second dielectric layer over the charge storage layer has a first portion that is thicker than a second portion to selectively control the charge tunneling.
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Chindalore Gowrishankar L.
Swift Craig T.
Chiu Joanna G.
Freescale Semiconductor Inc.
King Robert L.
Luu Pho M.
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