Method for multiple spacer width control

Details Method for multiple spacer width control Method for multiple spacer width control

2007-02-13

2007-02-13

Goudreau, George A. (Department: 1763)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S700000, C438S725000, C438S738000

Reexamination Certificate

active

10435009

ABSTRACT:
A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.

REFERENCES:
patent: 5783475 (1998-07-01), Ramaswami
patent: 6541328 (2003-04-01), Whang et al.
patent: 2002/0195686 (2002-12-01), Kim et al.
patent: 2004/0137373 (2004-07-01), Lei et al.

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